| Message ID | 8624FC902C662B4D9D77440AF5EA66252C5AF26C@temmail01.mytem.ch |
|---|---|
| State | Not Applicable |
| Delegated to: | Stefano Babic |
| Headers | show |
Hi Peter, On 24/11/2015 15:38, Bärtsch Peter wrote: > Hello Stefano, > > > > I have seen , that my patch already exist :o but not active in master > branch. > > Follow patch is the original from Ye.Le If you take a patch from someone else, you cannot change author. Patch was ok, but it was part of a series where some changes were requested. Anyway, patch is orthogonal to the other ones. I pick it up, of course the one from Ye. Best regards, Stefano Babic > > > > Kind regards > > Peter Bärtsch > > > > > > On mx6sx, the CCM register bits for GPMI are different as other > > mx6 platforms. Modify the GPMI clock function to support mx6sx. > > > > > > Signed-off-by: Ye.Li <b37...@freescale.com> > > --- > > arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++ > > 1 files changed, 12 insertions(+), 0 deletions(-) > > > > diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c > > index fd57f22..ce7f0f7 100644 > > --- a/arch/arm/cpu/armv7/mx6/clock.c > > +++ b/arch/arm/cpu/armv7/mx6/clock.c > > @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg) > > MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | > > MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); > > +#if defined(CONFIG_MX6SX) > > + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); > > + > > + clrsetbits_le32(&imx_ccm->cs2cdr, > > + MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | > > + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | > > + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK, > > + cfg); > > + > > + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); > > +#else > > clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); > > clrsetbits_le32(&imx_ccm->cs2cdr, > > @@ -56,6 +67,7 @@ void setup_gpmi_io_clk(u32 cfg) > > cfg); > > setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); > > +#endif > > setbits_le32(&imx_ccm->CCGR4, > > MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | > > MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | > > -- > > >
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index fd57f22..ce7f0f7 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg) MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK); +#if defined(CONFIG_MX6SX) + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); + + clrsetbits_le32(&imx_ccm->cs2cdr, + MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK | + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK, + cfg); + + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK); +#else clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); clrsetbits_le32(&imx_ccm->cs2cdr, @@ -56,6 +67,7 @@ void setup_gpmi_io_clk(u32 cfg) cfg);
Hello Stefano, I have seen , that my patch already exist :o but not active in master branch. Follow patch is the original from Ye.Le Kind regards Peter Bärtsch On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx. Signed-off-by: Ye.Li <b37...@freescale.com> --- arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); +#endif setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | --