Patchwork [08/16] Pass IRQ object on handler invocation

login
register
mail settings
Submitter Jan Kiszka
Date June 6, 2010, 8:10 a.m.
Message ID <1c026e117c46a23d3c4c1335d6407388de405f5d.1275811861.git.jan.kiszka@web.de>
Download mbox | patch
Permalink /patch/54815/
State New
Headers show

Comments

Jan Kiszka - June 6, 2010, 8:10 a.m.
From: Jan Kiszka <jan.kiszka@siemens.com>

Pass the qemu_irq object to its handler when delivering an event. This
enables the handler to invoke optional services that require an object
reference. Will be used for IRQs with attached messages.

There are a few direct handler calls. So far we simply pass NULL as IRQ
object. Once those handlers want to make use of the object, the direct
callers need to obtain and forward a proper reference.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 hw/acpi_piix4.c         |    3 ++-
 hw/apic.h               |    1 -
 hw/arm11mpcore.c        |   12 ++++++------
 hw/arm_gic.c            |   18 +++++++++---------
 hw/arm_pic.c            |    6 +++---
 hw/arm_timer.c          |    4 ++--
 hw/bitbang_i2c.c        |    4 ++--
 hw/bt-hci-csr.c         |    2 +-
 hw/cbus.c               |    6 +++---
 hw/cris_pic_cpu.c       |    4 ++--
 hw/esp.c                |    2 +-
 hw/etraxfs_pic.c        |   16 ++++++++--------
 hw/fdc.c                |    2 +-
 hw/heathrow_pic.c       |    3 ++-
 hw/i8259.c              |   14 +++++++-------
 hw/ide/cmd646.c         |    2 +-
 hw/ide/microdrive.c     |    2 +-
 hw/integratorcp.c       |   10 +++++-----
 hw/ioapic.c             |    2 +-
 hw/irq.c                |   13 ++++++-------
 hw/irq.h                |    4 +---
 hw/lance.c              |    2 +-
 hw/max7310.c            |    2 +-
 hw/mcf5206.c            |    6 +++---
 hw/mcf_intc.c           |   14 ++++++++------
 hw/microblaze_pic_cpu.c |    5 +++--
 hw/mips_int.c           |   10 +++++-----
 hw/mips_jazz.c          |    2 +-
 hw/mips_malta.c         |    2 +-
 hw/mst_fpga.c           |   10 +++++-----
 hw/musicpal.c           |   16 +++++++++-------
 hw/nseries.c            |    4 ++--
 hw/omap.h               |    2 +-
 hw/omap1.c              |   34 ++++++++++++++++++----------------
 hw/omap2.c              |    8 +++++---
 hw/omap_dma.c           |    8 ++++----
 hw/omap_mmc.c           |    2 +-
 hw/openpic.c            |    6 +++---
 hw/palm.c               |    2 +-
 hw/pc.c                 |   15 ++++++++-------
 hw/pc.h                 |    8 +++-----
 hw/pci.c                |    4 ++--
 hw/pl061.c              |    4 ++--
 hw/pl190.c              |    6 +++---
 hw/ppc.c                |    8 ++++----
 hw/ppc4xx_devs.c        |    2 +-
 hw/ppc_prep.c           |    2 +-
 hw/pxa2xx.c             |    2 +-
 hw/pxa2xx_gpio.c        |    2 +-
 hw/pxa2xx_pcmcia.c      |    3 ++-
 hw/pxa2xx_pic.c         |   10 +++++-----
 hw/r2d.c                |    2 +-
 hw/rc4030.c             |    7 ++++---
 hw/sbi.c                |    2 +-
 hw/sh_intc.c            |    4 ++--
 hw/sh_intc.h            |    2 +-
 hw/sharpsl.h            |    1 -
 hw/slavio_intctl.c      |   16 ++++++++--------
 hw/slavio_misc.c        |    3 ++-
 hw/sparc32_dma.c        |    2 +-
 hw/spitz.c              |   14 ++++++++------
 hw/ssd0323.c            |    2 +-
 hw/stellaris.c          |    6 ++++--
 hw/sun4c_intctl.c       |    8 ++++----
 hw/sun4m.c              |   14 +++++++-------
 hw/sun4u.c              |   12 ++++++------
 hw/syborg_interrupt.c   |    8 ++++----
 hw/tc6393xb.c           |    7 ++++---
 hw/tosa.c               |    2 +-
 hw/tusb6010.c           |    3 ++-
 hw/twl92230.c           |    5 +++--
 hw/versatilepb.c        |   10 +++++-----
 hw/xilinx_intc.c        |    8 ++++----
 hw/zaurus.c             |    2 +-
 74 files changed, 243 insertions(+), 228 deletions(-)

Patch

diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c
index 0fce958..a2268b2 100644
--- a/hw/acpi_piix4.c
+++ b/hw/acpi_piix4.c
@@ -316,7 +316,8 @@  static void piix4_reset(void *opaque)
     }
 }
 
-static void piix4_powerdown(void *opaque, int irq, int power_failing)
+static void piix4_powerdown(qemu_irq irq, void *opaque, int n,
+                            int power_failing)
 {
     PIIX4PMState *s = opaque;
 
diff --git a/hw/apic.h b/hw/apic.h
index 132fcab..e1954f4 100644
--- a/hw/apic.h
+++ b/hw/apic.h
@@ -11,7 +11,6 @@  int apic_accept_pic_intr(CPUState *env);
 void apic_deliver_pic_intr(CPUState *env, int level);
 int apic_get_interrupt(CPUState *env);
 qemu_irq *ioapic_init(void);
-void ioapic_set_irq(void *opaque, int vector, int level);
 void apic_reset_irq_delivered(void);
 int apic_get_irq_delivered(void);
 
diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
index 3bbd885..694e238 100644
--- a/hw/arm11mpcore.c
+++ b/hw/arm11mpcore.c
@@ -32,18 +32,18 @@  static const int mpcore_irq_map[32] = {
     -1, -1, -1, -1,  9,  3, -1, -1,
 };
 
-static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
+static void mpcore_rirq_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
     int i;
 
     for (i = 0; i < 4; i++) {
-        qemu_set_irq(s->rvic[i][irq], level);
+        qemu_set_irq(s->rvic[i][n], level);
     }
-    if (irq < 32) {
-        irq = mpcore_irq_map[irq];
-        if (irq >= 0) {
-            qemu_set_irq(s->cpuic[irq], level);
+    if (n < 32) {
+        n = mpcore_irq_map[n];
+        if (n >= 0) {
+            qemu_set_irq(s->cpuic[n], level);
         }
     }
 }
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index c4afc6a..90aeb09 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -161,22 +161,22 @@  gic_set_pending_private(gic_state *s, int cpu, int irq)
 }
 
 /* Process a change in an external IRQ input.  */
-static void gic_set_irq(void *opaque, int irq, int level)
+static void gic_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     gic_state *s = (gic_state *)opaque;
     /* The first external input line is internal interrupt 32.  */
-    irq += 32;
-    if (level == GIC_TEST_LEVEL(irq, ALL_CPU_MASK))
+    n += 32;
+    if (level == GIC_TEST_LEVEL(n, ALL_CPU_MASK)) {
         return;
-
+    }
     if (level) {
-        GIC_SET_LEVEL(irq, ALL_CPU_MASK);
-        if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
-            DPRINTF("Set %d pending mask %x\n", irq, GIC_TARGET(irq));
-            GIC_SET_PENDING(irq, GIC_TARGET(irq));
+        GIC_SET_LEVEL(n, ALL_CPU_MASK);
+        if (GIC_TEST_TRIGGER(n) || GIC_TEST_ENABLED(n)) {
+            DPRINTF("Set %d pending mask %x\n", n, GIC_TARGET(n));
+            GIC_SET_PENDING(n, GIC_TARGET(n));
         }
     } else {
-        GIC_CLEAR_LEVEL(irq, ALL_CPU_MASK);
+        GIC_CLEAR_LEVEL(n, ALL_CPU_MASK);
     }
     gic_update(s);
 }
diff --git a/hw/arm_pic.c b/hw/arm_pic.c
index f44568c..d6f8acc 100644
--- a/hw/arm_pic.c
+++ b/hw/arm_pic.c
@@ -22,10 +22,10 @@  void irq_info(Monitor *mon)
 
 
 /* Input 0 is IRQ and input 1 is FIQ.  */
-static void arm_pic_cpu_handler(void *opaque, int irq, int level)
+static void arm_pic_cpu_handler(qemu_irq irq, void *opaque, int n, int level)
 {
     CPUState *env = (CPUState *)opaque;
-    switch (irq) {
+    switch (n) {
     case ARM_PIC_CPU_IRQ:
         if (level)
             cpu_interrupt(env, CPU_INTERRUPT_HARD);
@@ -39,7 +39,7 @@  static void arm_pic_cpu_handler(void *opaque, int irq, int level)
             cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ);
         break;
     default:
-        hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", irq);
+        hw_error("arm_pic_cpu_handler: Bad interrput line %d\n", n);
     }
 }
 
diff --git a/hw/arm_timer.c b/hw/arm_timer.c
index 9073ffc..074254a 100644
--- a/hw/arm_timer.c
+++ b/hw/arm_timer.c
@@ -191,11 +191,11 @@  typedef struct {
 } sp804_state;
 
 /* Merge the IRQs from the two component devices.  */
-static void sp804_set_irq(void *opaque, int irq, int level)
+static void sp804_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     sp804_state *s = (sp804_state *)opaque;
 
-    s->level[irq] = level;
+    s->level[n] = level;
     qemu_set_irq(s->irq, s->level[0] || s->level[1]);
 }
 
diff --git a/hw/bitbang_i2c.c b/hw/bitbang_i2c.c
index 4ee99a1..d4708d2 100644
--- a/hw/bitbang_i2c.c
+++ b/hw/bitbang_i2c.c
@@ -186,11 +186,11 @@  typedef struct {
     qemu_irq out;
 } GPIOI2CState;
 
-static void bitbang_i2c_gpio_set(void *opaque, int irq, int level)
+static void bitbang_i2c_gpio_set(qemu_irq irq, void *opaque, int n, int level)
 {
     GPIOI2CState *s = opaque;
 
-    level = bitbang_i2c_set(s->bitbang, irq, level);
+    level = bitbang_i2c_set(s->bitbang, n, level);
     if (level != s->last_level) {
         s->last_level = level;
         qemu_set_irq(s->out, level);
diff --git a/hw/bt-hci-csr.c b/hw/bt-hci-csr.c
index 982577d..1d63a5d 100644
--- a/hw/bt-hci-csr.c
+++ b/hw/bt-hci-csr.c
@@ -406,7 +406,7 @@  static void csrhci_out_tick(void *opaque)
     csrhci_fifo_wake((struct csrhci_s *) opaque);
 }
 
-static void csrhci_pins(void *opaque, int line, int level)
+static void csrhci_pins(qemu_irq irq, void *opaque, int line, int level)
 {
     struct csrhci_s *s = (struct csrhci_s *) opaque;
     int state = s->pin_state;
diff --git a/hw/cbus.c b/hw/cbus.c
index 8ae24e0..fa01ec0 100644
--- a/hw/cbus.c
+++ b/hw/cbus.c
@@ -93,7 +93,7 @@  static void cbus_cycle(CBusPriv *s)
     }
 }
 
-static void cbus_clk(void *opaque, int line, int level)
+static void cbus_clk(qemu_irq irq, void *opaque, int line, int level)
 {
     CBusPriv *s = (CBusPriv *) opaque;
 
@@ -110,14 +110,14 @@  static void cbus_clk(void *opaque, int line, int level)
     s->clk = level;
 }
 
-static void cbus_dat(void *opaque, int line, int level)
+static void cbus_dat(qemu_irq irq, void *opaque, int line, int level)
 {
     CBusPriv *s = (CBusPriv *) opaque;
 
     s->dat = level;
 }
 
-static void cbus_sel(void *opaque, int line, int level)
+static void cbus_sel(qemu_irq irq, void *opaque, int line, int level)
 {
     CBusPriv *s = (CBusPriv *) opaque;
 
diff --git a/hw/cris_pic_cpu.c b/hw/cris_pic_cpu.c
index a92d445..f85ac24 100644
--- a/hw/cris_pic_cpu.c
+++ b/hw/cris_pic_cpu.c
@@ -33,10 +33,10 @@  void pic_info(Monitor *mon)
 void irq_info(Monitor *mon)
 {}
 
-static void cris_pic_cpu_handler(void *opaque, int irq, int level)
+static void cris_pic_cpu_handler(qemu_irq irq, void *opaque, int n, int level)
 {
     CPUState *env = (CPUState *)opaque;
-    int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
+    int type = n ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
 
     if (level)
         cpu_interrupt(env, type);
diff --git a/hw/esp.c b/hw/esp.c
index 0a8cf6e..a657eba 100644
--- a/hw/esp.c
+++ b/hw/esp.c
@@ -435,7 +435,7 @@  static void esp_reset(DeviceState *d)
     s->rregs[ESP_CFG1] = 7;
 }
 
-static void parent_esp_reset(void *opaque, int irq, int level)
+static void parent_esp_reset(qemu_irq irq, void *opaque, int n, int level)
 {
     if (level)
         esp_reset(opaque);
diff --git a/hw/etraxfs_pic.c b/hw/etraxfs_pic.c
index b2c4859..c612316 100644
--- a/hw/etraxfs_pic.c
+++ b/hw/etraxfs_pic.c
@@ -123,16 +123,16 @@  static void nmi_handler(void *opaque, int irq, int level)
     qemu_set_irq(fs->parent_nmi, !!fs->regs[R_R_NMI]);
 }
 
-static void irq_handler(void *opaque, int irq, int level)
-{   
+static void irq_handler(qemu_irq irq, void *opaque, int n, int level)
+{
     struct etrax_pic *fs = (void *)opaque;
 
-    if (irq >= 30)
-        return nmi_handler(opaque, irq, level);
-
-    irq -= 1;
-    fs->regs[R_R_VECT] &= ~(1 << irq);
-    fs->regs[R_R_VECT] |= (!!level << irq);
+    if (n >= 30) {
+        return nmi_handler(opaque, n, level);
+    }
+    n -= 1;
+    fs->regs[R_R_VECT] &= ~(1 << n);
+    fs->regs[R_R_VECT] |= (!!level << n);
     pic_update(fs);
 }
 
diff --git a/hw/fdc.c b/hw/fdc.c
index 6306496..d884d33 100644
--- a/hw/fdc.c
+++ b/hw/fdc.c
@@ -716,7 +716,7 @@  static void fdctrl_external_reset_isa(DeviceState *d)
     fdctrl_reset(s, 0);
 }
 
-static void fdctrl_handle_tc(void *opaque, int irq, int level)
+static void fdctrl_handle_tc(qemu_irq irq, void *opaque, int n, int level)
 {
     //FDCtrl *s = opaque;
 
diff --git a/hw/heathrow_pic.c b/hw/heathrow_pic.c
index 5e27021..1492312 100644
--- a/hw/heathrow_pic.c
+++ b/hw/heathrow_pic.c
@@ -135,7 +135,8 @@  static CPUReadMemoryFunc * const pic_read[] = {
 };
 
 
-static void heathrow_pic_set_irq(void *opaque, int num, int level)
+static void heathrow_pic_set_irq(qemu_irq irq, void *opaque, int num,
+                                 int level)
 {
     HeathrowPICS *s = opaque;
     HeathrowPIC *pic;
diff --git a/hw/i8259.c b/hw/i8259.c
index a995280..f743ee8 100644
--- a/hw/i8259.c
+++ b/hw/i8259.c
@@ -186,26 +186,26 @@  void pic_update_irq(PicState2 *s)
 int64_t irq_time[16];
 #endif
 
-static void i8259_set_irq(void *opaque, int irq, int level)
+static void i8259_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     PicState2 *s = opaque;
 
 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
-    if (level != irq_level[irq]) {
-        DPRINTF("i8259_set_irq: irq=%d level=%d\n", irq, level);
-        irq_level[irq] = level;
+    if (level != irq_level[n]) {
+        DPRINTF("i8259_set_irq: irq=%d level=%d\n", n, level);
+        irq_level[n] = level;
 #ifdef DEBUG_IRQ_COUNT
 	if (level == 1)
-	    irq_count[irq]++;
+	    irq_count[n]++;
 #endif
     }
 #endif
 #ifdef DEBUG_IRQ_LATENCY
     if (level) {
-        irq_time[irq] = qemu_get_clock(vm_clock);
+        irq_time[n] = qemu_get_clock(vm_clock);
     }
 #endif
-    pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
+    pic_set_irq1(&s->pics[n >> 3], n & 7, level);
     pic_update_irq(s);
 }
 
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index cdcc9bf..8ca55ea 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -202,7 +202,7 @@  static void cmd646_update_irq(PCIIDEState *d)
 }
 
 /* the PCI irq level is the logical OR of the two channels */
-static void cmd646_set_irq(void *opaque, int channel, int level)
+static void cmd646_set_irq(qemu_irq irq, void *opaque, int channel, int level)
 {
     PCIIDEState *d = opaque;
     int irq_mask;
diff --git a/hw/ide/microdrive.c b/hw/ide/microdrive.c
index bfdb8c8..c852665 100644
--- a/hw/ide/microdrive.c
+++ b/hw/ide/microdrive.c
@@ -92,7 +92,7 @@  static inline void md_interrupt_update(MicroDriveState *s)
                     !(s->opt & OPT_SRESET));
 }
 
-static void md_set_irq(void *opaque, int irq, int level)
+static void md_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     MicroDriveState *s = opaque;
     if (level)
diff --git a/hw/integratorcp.c b/hw/integratorcp.c
index bee8298..db78f04 100644
--- a/hw/integratorcp.c
+++ b/hw/integratorcp.c
@@ -286,13 +286,13 @@  static void icp_pic_update(icp_pic_state *s)
     qemu_set_irq(s->parent_fiq, flags != 0);
 }
 
-static void icp_pic_set_irq(void *opaque, int irq, int level)
+static void icp_pic_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     icp_pic_state *s = (icp_pic_state *)opaque;
     if (level)
-        s->level |= 1 << irq;
+        s->level |= 1 << n;
     else
-        s->level &= ~(1 << irq);
+        s->level &= ~(1 << n);
     icp_pic_update(s);
 }
 
@@ -338,11 +338,11 @@  static void icp_pic_write(void *opaque, target_phys_addr_t offset,
         break;
     case 4: /* INT_SOFTSET */
         if (value & 1)
-            icp_pic_set_irq(s, 0, 1);
+            icp_pic_set_irq(NULL, s, 0, 1);
         break;
     case 5: /* INT_SOFTCLR */
         if (value & 1)
-            icp_pic_set_irq(s, 0, 0);
+            icp_pic_set_irq(NULL, s, 0, 0);
         break;
     case 10: /* FRQ_ENABLESET */
         s->fiq_enabled |= value;
diff --git a/hw/ioapic.c b/hw/ioapic.c
index 335da6e..d818573 100644
--- a/hw/ioapic.c
+++ b/hw/ioapic.c
@@ -94,7 +94,7 @@  static void ioapic_service(IOAPICState *s)
     }
 }
 
-void ioapic_set_irq(void *opaque, int vector, int level)
+static void ioapic_set_irq(qemu_irq irq, void *opaque, int vector, int level)
 {
     IOAPICState *s = opaque;
 
diff --git a/hw/irq.c b/hw/irq.c
index 7703f62..24fb09d 100644
--- a/hw/irq.c
+++ b/hw/irq.c
@@ -32,10 +32,9 @@  struct IRQState {
 
 void qemu_set_irq(qemu_irq irq, int level)
 {
-    if (!irq)
-        return;
-
-    irq->handler(irq->opaque, irq->n, level);
+    if (irq) {
+        irq->handler(irq, irq->opaque, irq->n, level);
+    }
 }
 
 qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n)
@@ -62,11 +61,11 @@  void qemu_free_irqs(qemu_irq *s)
     qemu_free(s);
 }
 
-static void qemu_notirq(void *opaque, int line, int level)
+static void qemu_notirq(qemu_irq irq, void *opaque, int line, int level)
 {
-    struct IRQState *irq = opaque;
+    struct IRQState *inv_irq = opaque;
 
-    irq->handler(irq->opaque, irq->n, !level);
+    inv_irq->handler(inv_irq, inv_irq->opaque, inv_irq->n, !level);
 }
 
 qemu_irq qemu_irq_invert(qemu_irq irq)
diff --git a/hw/irq.h b/hw/irq.h
index 5daae44..d0f83e3 100644
--- a/hw/irq.h
+++ b/hw/irq.h
@@ -3,9 +3,7 @@ 
 
 /* Generic IRQ/GPIO pin infrastructure.  */
 
-/* FIXME: Rmove one of these.  */
-typedef void (*qemu_irq_handler)(void *opaque, int n, int level);
-typedef void SetIRQFunc(void *opaque, int irq_num, int level);
+typedef void (*qemu_irq_handler)(qemu_irq irq, void *opaque, int n, int level);
 
 void qemu_set_irq(qemu_irq irq, int level);
 
diff --git a/hw/lance.c b/hw/lance.c
index b6b04dd..de9e9bd 100644
--- a/hw/lance.c
+++ b/hw/lance.c
@@ -48,7 +48,7 @@  typedef struct {
     PCNetState state;
 } SysBusPCNetState;
 
-static void parent_lance_reset(void *opaque, int irq, int level)
+static void parent_lance_reset(qemu_irq irq, void *opaque, int n, int level)
 {
     SysBusPCNetState *d = opaque;
     if (level)
diff --git a/hw/max7310.c b/hw/max7310.c
index c302eb6..dc0f8ea 100644
--- a/hw/max7310.c
+++ b/hw/max7310.c
@@ -161,7 +161,7 @@  static const VMStateDescription vmstate_max7310 = {
     }
 };
 
-static void max7310_gpio_set(void *opaque, int line, int level)
+static void max7310_gpio_set(qemu_irq irq, void *opaque, int line, int level)
 {
     MAX7310State *s = (MAX7310State *) opaque;
     if (line >= ARRAY_SIZE(s->handler) || line  < 0)
diff --git a/hw/mcf5206.c b/hw/mcf5206.c
index c107de8..eca6e63 100644
--- a/hw/mcf5206.c
+++ b/hw/mcf5206.c
@@ -226,13 +226,13 @@  static void m5206_mbar_update(m5206_mbar_state *s)
     m68k_set_irq_level(s->env, level, vector);
 }
 
-static void m5206_mbar_set_irq(void *opaque, int irq, int level)
+static void m5206_mbar_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     m5206_mbar_state *s = (m5206_mbar_state *)opaque;
     if (level) {
-        s->ipr |= 1 << irq;
+        s->ipr |= 1 << n;
     } else {
-        s->ipr &= ~(1 << irq);
+        s->ipr &= ~(1 << n);
     }
     m5206_mbar_update(s);
 }
diff --git a/hw/mcf_intc.c b/hw/mcf_intc.c
index f01bd32..620c10e 100644
--- a/hw/mcf_intc.c
+++ b/hw/mcf_intc.c
@@ -105,15 +105,17 @@  static void mcf_intc_write(void *opaque, target_phys_addr_t addr, uint32_t val)
     mcf_intc_update(s);
 }
 
-static void mcf_intc_set_irq(void *opaque, int irq, int level)
+static void mcf_intc_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     mcf_intc_state *s = (mcf_intc_state *)opaque;
-    if (irq >= 64)
+    if (n >= 64) {
         return;
-    if (level)
-        s->ipr |= 1ull << irq;
-    else
-        s->ipr &= ~(1ull << irq);
+    }
+    if (level) {
+        s->ipr |= 1ull << n;
+    } else {
+        s->ipr &= ~(1ull << n);
+    }
     mcf_intc_update(s);
 }
 
diff --git a/hw/microblaze_pic_cpu.c b/hw/microblaze_pic_cpu.c
index 7c59382..200832d 100644
--- a/hw/microblaze_pic_cpu.c
+++ b/hw/microblaze_pic_cpu.c
@@ -32,10 +32,11 @@  void pic_info(Monitor *mon)
 void irq_info(Monitor *mon)
 {}
 
-static void microblaze_pic_cpu_handler(void *opaque, int irq, int level)
+static void microblaze_pic_cpu_handler(qemu_irq irq, void *opaque, int n,
+                                       int level)
 {
     CPUState *env = (CPUState *)opaque;
-    int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
+    int type = n ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
 
     if (level)
         cpu_interrupt(env, type);
diff --git a/hw/mips_int.c b/hw/mips_int.c
index c30954c..434b47a 100644
--- a/hw/mips_int.c
+++ b/hw/mips_int.c
@@ -40,17 +40,17 @@  void cpu_mips_update_irq(CPUState *env)
         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 }
 
-static void cpu_mips_irq_request(void *opaque, int irq, int level)
+static void cpu_mips_irq_request(qemu_irq irq, void *opaque, int n, int level)
 {
     CPUState *env = (CPUState *)opaque;
 
-    if (irq < 0 || irq > 7)
+    if (n < 0 || n > 7) {
         return;
-
+    }
     if (level) {
-        env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
+        env->CP0_Cause |= 1 << (n + CP0Ca_IP);
     } else {
-        env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
+        env->CP0_Cause &= ~(1 << (n + CP0Ca_IP));
     }
     cpu_mips_update_irq(env);
 }
diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c
index ead3a00..da1bf6e 100644
--- a/hw/mips_jazz.c
+++ b/hw/mips_jazz.c
@@ -114,7 +114,7 @@  static void audio_init(qemu_irq *pic)
 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
 
-static void cpu_request_exit(void *opaque, int irq, int level)
+static void cpu_request_exit(qemu_irq irq, void *opaque, int n, int level)
 {
     CPUState *env = cpu_single_env;
 
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index a8f9d15..bd86636 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -763,7 +763,7 @@  static void main_cpu_reset(void *opaque)
     }
 }
 
-static void cpu_request_exit(void *opaque, int irq, int level)
+static void cpu_request_exit(qemu_irq irq, void *opaque, int n, int level)
 {
     CPUState *env = cpu_single_env;
 
diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index 1b6cb77..6d5fc8f 100644
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -61,17 +61,17 @@  mst_fpga_update_gpio(mst_irq_state *s)
 }
 
 static void
-mst_fpga_set_irq(void *opaque, int irq, int level)
+mst_fpga_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
 	mst_irq_state *s = (mst_irq_state *)opaque;
 
 	if (level)
-		s->prev_level |= 1u << irq;
+		s->prev_level |= 1u << n;
 	else
-		s->prev_level &= ~(1u << irq);
+		s->prev_level &= ~(1u << n);
 
-	if(s->intmskena & (1u << irq)) {
-		s->intsetclr = 1u << irq;
+	if (s->intmskena & (1u << n)) {
+		s->intsetclr = 1u << n;
 		qemu_set_irq(s->parent[0], level);
 	}
 }
diff --git a/hw/musicpal.c b/hw/musicpal.c
index d44c5a0..fa86180 100644
--- a/hw/musicpal.c
+++ b/hw/musicpal.c
@@ -519,11 +519,12 @@  static void lcd_invalidate(void *opaque)
 {
 }
 
-static void musicpal_lcd_gpio_brigthness_in(void *opaque, int irq, int level)
+static void musicpal_lcd_gpio_brigthness_in(qemu_irq irq, void *opaque, int n,
+                                            int level)
 {
     musicpal_lcd_state *s = opaque;
-    s->brightness &= ~(1 << irq);
-    s->brightness |= level << irq;
+    s->brightness &= ~(1 << n);
+    s->brightness |= level << n;
 }
 
 static uint32_t musicpal_lcd_read(void *opaque, target_phys_addr_t offset)
@@ -652,14 +653,14 @@  static void mv88w8618_pic_update(mv88w8618_pic_state *s)
     qemu_set_irq(s->parent_irq, (s->level & s->enabled));
 }
 
-static void mv88w8618_pic_set_irq(void *opaque, int irq, int level)
+static void mv88w8618_pic_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     mv88w8618_pic_state *s = opaque;
 
     if (level) {
-        s->level |= 1 << irq;
+        s->level |= 1 << n;
     } else {
-        s->level &= ~(1 << irq);
+        s->level &= ~(1 << n);
     }
     mv88w8618_pic_update(s);
 }
@@ -1165,7 +1166,8 @@  static void musicpal_gpio_brightness_update(musicpal_gpio_state *s) {
     }
 }
 
-static void musicpal_gpio_pin_event(void *opaque, int pin, int level)
+static void musicpal_gpio_pin_event(qemu_irq irq, void *opaque, int pin,
+                                    int level)
 {
     musicpal_gpio_state *s = opaque;
     uint32_t mask = 1 << pin;
diff --git a/hw/nseries.c b/hw/nseries.c
index 04a028d..21cbf6c 100644
--- a/hw/nseries.c
+++ b/hw/nseries.c
@@ -122,7 +122,7 @@  struct n800_s {
 
 #define N8X0_BD_ADDR			0x00, 0x1a, 0x89, 0x9e, 0x3e, 0x81
 
-static void n800_mmc_cs_cb(void *opaque, int line, int level)
+static void n800_mmc_cs_cb(qemu_irq irq, void *opaque, int line, int level)
 {
     /* TODO: this seems to actually be connected to the menelaus, to
      * which also both MMC slots connect.  */
@@ -754,7 +754,7 @@  static void n8x0_uart_setup(struct n800_s *s)
     omap_uart_attach(s->cpu->uart[BT_UART], radio);
 }
 
-static void n8x0_usb_power_cb(void *opaque, int line, int level)
+static void n8x0_usb_power_cb(qemu_irq irq, void *opaque, int line, int level)
 {
     struct n800_s *s = opaque;
 
diff --git a/hw/omap.h b/hw/omap.h
index d305779..4e31860 100644
--- a/hw/omap.h
+++ b/hw/omap.h
@@ -979,7 +979,7 @@  uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr);
 void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
                 uint32_t value);
 
-void omap_mpu_wakeup(void *opaque, int irq, int req);
+void omap_mpu_wakeup(qemu_irq irq, void *opaque, int n, int req);
 
 # define OMAP_BAD_REG(paddr)		\
         fprintf(stderr, "%s: Bad register " OMAP_FMT_plx "\n",	\
diff --git a/hw/omap1.c b/hw/omap1.c
index 8649dbd..cf2191d 100644
--- a/hw/omap1.c
+++ b/hw/omap1.c
@@ -150,13 +150,13 @@  static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
 #define INT_FALLING_EDGE	0
 #define INT_LOW_LEVEL		1
 
-static void omap_set_intr(void *opaque, int irq, int req)
+static void omap_set_intr(qemu_irq irq, void *opaque, int line, int req)
 {
     struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
     uint32_t rise;
 
-    struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
-    int n = irq & 31;
+    struct omap_intr_handler_bank_s *bank = &ih->bank[line >> 5];
+    int n = line & 31;
 
     if (req) {
         rise = ~bank->irqs & (1 << n);
@@ -177,13 +177,13 @@  static void omap_set_intr(void *opaque, int irq, int req)
 }
 
 /* Simplified version with no edge detection */
-static void omap_set_intr_noedge(void *opaque, int irq, int req)
+static void omap_set_intr_noedge(qemu_irq irq, void *opaque, int line, int req)
 {
     struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
     uint32_t rise;
 
-    struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
-    int n = irq & 31;
+    struct omap_intr_handler_bank_s *bank = &ih->bank[line >> 5];
+    int n = line & 31;
 
     if (req) {
         rise = ~bank->inputs & (1 << n);
@@ -358,7 +358,7 @@  static void omap_inth_write(void *opaque, target_phys_addr_t addr,
     case 0x9c:	/* ISR */
         for (i = 0; i < 32; i ++)
             if (value & (1 << i)) {
-                omap_set_intr(s, 32 * bank_no + i, 1);
+                omap_set_intr(NULL, s, 32 * bank_no + i, 1);
                 return;
             }
         return;
@@ -732,7 +732,7 @@  static void omap_timer_tick(void *opaque)
     omap_timer_update(timer);
 }
 
-static void omap_timer_clk_update(void *opaque, int line, int on)
+static void omap_timer_clk_update(qemu_irq irq, void *opaque, int line, int on)
 {
     struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
 
@@ -2556,7 +2556,7 @@  struct omap_mpuio_s {
     int clk;
 };
 
-static void omap_mpuio_set(void *opaque, int line, int level)
+static void omap_mpuio_set(qemu_irq irq, void *opaque, int line, int level)
 {
     struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
     uint16_t prev = s->inputs;
@@ -2747,7 +2747,7 @@  static void omap_mpuio_reset(struct omap_mpuio_s *s)
     s->clk = 1;
 }
 
-static void omap_mpuio_onoff(void *opaque, int line, int on)
+static void omap_mpuio_onoff(qemu_irq irq, void *opaque, int line, int on)
 {
     struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
 
@@ -2819,7 +2819,7 @@  struct omap_gpio_s {
     uint16_t pins;
 };
 
-static void omap_gpio_set(void *opaque, int line, int level)
+static void omap_gpio_set(qemu_irq irq, void *opaque, int line, int level)
 {
     struct omap_gpio_s *s = (struct omap_gpio_s *) opaque;
     uint16_t prev = s->inputs;
@@ -3222,7 +3222,7 @@  static void omap_pwl_reset(struct omap_mpu_state_s *s)
     omap_pwl_update(s);
 }
 
-static void omap_pwl_clk_update(void *opaque, int line, int on)
+static void omap_pwl_clk_update(qemu_irq irq, void *opaque, int line, int on)
 {
     struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
 
@@ -4274,7 +4274,8 @@  struct omap_mcbsp_s *omap_mcbsp_init(target_phys_addr_t base,
     return s;
 }
 
-static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
+static void omap_mcbsp_i2s_swallow(qemu_irq irq, void *opaque, int line,
+                                   int level)
 {
     struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
 
@@ -4284,7 +4285,8 @@  static void omap_mcbsp_i2s_swallow(void *opaque, int line, int level)
     }
 }
 
-static void omap_mcbsp_i2s_start(void *opaque, int line, int level)
+static void omap_mcbsp_i2s_start(qemu_irq irq, void *opaque, int line,
+                                 int level)
 {
     struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
 
@@ -4421,7 +4423,7 @@  static CPUWriteMemoryFunc * const omap_lpg_writefn[] = {
     omap_badwidth_write8,
 };
 
-static void omap_lpg_clk_update(void *opaque, int line, int on)
+static void omap_lpg_clk_update(qemu_irq irq, void *opaque, int line, int on)
 {
     struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
 
@@ -4560,7 +4562,7 @@  static void omap_setup_dsp_mapping(const struct omap_map_s *map)
     }
 }
 
-void omap_mpu_wakeup(void *opaque, int irq, int req)
+void omap_mpu_wakeup(qemu_irq irq, void *opaque, int n, int req)
 {
     struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
 
diff --git a/hw/omap2.c b/hw/omap2.c
index bd1b35e..ec73775 100644
--- a/hw/omap2.c
+++ b/hw/omap2.c
@@ -190,7 +190,7 @@  static void omap_gp_timer_match(void *opaque)
     omap_gp_timer_intr(timer, GPT_MAT_IT);
 }
 
-static void omap_gp_timer_input(void *opaque, int line, int on)
+static void omap_gp_timer_input(qemu_irq irq, void *opaque, int line, int on)
 {
     struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
     int trigger;
@@ -220,7 +220,8 @@  static void omap_gp_timer_input(void *opaque, int line, int on)
     }
 }
 
-static void omap_gp_timer_clk_update(void *opaque, int line, int on)
+static void omap_gp_timer_clk_update(qemu_irq irq, void *opaque, int line,
+                                     int on)
 {
     struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
 
@@ -625,7 +626,8 @@  static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line)
     omap_gpio_module_wake(s, line);
 }
 
-static void omap_gpio_module_set(void *opaque, int line, int level)
+static void omap_gpio_module_set(qemu_irq irq, void *opaque, int line,
+                                 int level)
 {
     struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
 
diff --git a/hw/omap_dma.c b/hw/omap_dma.c
index 3e718ba..4006d81 100644
--- a/hw/omap_dma.c
+++ b/hw/omap_dma.c
@@ -1542,7 +1542,7 @@  static CPUWriteMemoryFunc * const omap_dma_writefn[] = {
     omap_badwidth_write16,
 };
 
-static void omap_dma_request(void *opaque, int drq, int req)
+static void omap_dma_request(qemu_irq irq, void *opaque, int drq, int req)
 {
     struct omap_dma_s *s = (struct omap_dma_s *) opaque;
     /* The request pins are level triggered in QEMU.  */
@@ -1556,7 +1556,7 @@  static void omap_dma_request(void *opaque, int drq, int req)
 }
 
 /* XXX: this won't be needed once soc_dma knows about clocks.  */
-static void omap_dma_clk_update(void *opaque, int line, int on)
+static void omap_dma_clk_update(qemu_irq irq, void *opaque, int line, int on)
 {
     struct omap_dma_s *s = (struct omap_dma_s *) opaque;
     int i;
@@ -1656,7 +1656,7 @@  struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
     omap_dma_setcaps(s);
     omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
     omap_dma_reset(s->dma);
-    omap_dma_clk_update(s, 0, 1);
+    omap_dma_clk_update(NULL, s, 0, 1);
 
     iomemtype = cpu_register_io_memory(omap_dma_readfn,
                     omap_dma_writefn, s);
@@ -2063,7 +2063,7 @@  struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
     omap_dma_setcaps(s);
     omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
     omap_dma_reset(s->dma);
-    omap_dma_clk_update(s, 0, !!s->dma->freq);
+    omap_dma_clk_update(NULL, s, 0, !!s->dma->freq);
 
     iomemtype = cpu_register_io_memory(omap_dma4_readfn,
                     omap_dma4_writefn, s);
diff --git a/hw/omap_mmc.c b/hw/omap_mmc.c
index 15cbf06..ec8719e 100644
--- a/hw/omap_mmc.c
+++ b/hw/omap_mmc.c
@@ -552,7 +552,7 @@  static CPUWriteMemoryFunc * const omap_mmc_writefn[] = {
     omap_badwidth_write16,
 };
 
-static void omap_mmc_cover_cb(void *opaque, int line, int level)
+static void omap_mmc_cover_cb(qemu_irq irq, void *opaque, int line, int level)
 {
     struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
 
diff --git a/hw/openpic.c b/hw/openpic.c
index ac21993..74730ee 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -399,7 +399,7 @@  static void openpic_update_irq(openpic_t *opp, int n_IRQ)
     }
 }
 
-static void openpic_set_irq(void *opaque, int n_IRQ, int level)
+static void openpic_set_irq(qemu_irq irq, void *opaque, int n_IRQ, int level)
 {
     openpic_t *opp = opaque;
     IRQ_src_t *src;
@@ -832,8 +832,8 @@  static void openpic_cpu_write (void *opaque, target_phys_addr_t addr, uint32_t v
     case 0x70:
         idx = (addr - 0x40) >> 4;
         write_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE, val);
-        openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
-        openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
+        openpic_set_irq(NULL, opp, opp->irq_ipi0 + idx, 1);
+        openpic_set_irq(NULL, opp, opp->irq_ipi0 + idx, 0);
         break;
 #endif
     case 0x80: /* PCTP */
diff --git a/hw/palm.c b/hw/palm.c
index 8db133d..88448c2 100644
--- a/hw/palm.c
+++ b/hw/palm.c
@@ -131,7 +131,7 @@  static void palmte_button_event(void *opaque, int keycode)
                         !(keycode & 0x80));
 }
 
-static void palmte_onoff_gpios(void *opaque, int line, int level)
+static void palmte_onoff_gpios(qemu_irq irq, void *opaque, int line, int level)
 {
     switch (line) {
     case 0:
diff --git a/hw/pc.c b/hw/pc.c
index ae31e2e..20057ca 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -77,7 +77,7 @@  struct e820_table {
 
 static struct e820_table e820_table;
 
-void isa_irq_handler(void *opaque, int n, int level)
+void isa_irq_handler(qemu_irq irq, void *opaque, int n, int level)
 {
     IsaIrqState *isa = (IsaIrqState *)opaque;
 
@@ -158,11 +158,11 @@  int cpu_get_pic_interrupt(CPUState *env)
     return intno;
 }
 
-static void pic_irq_request(void *opaque, int irq, int level)
+static void pic_irq_request(qemu_irq irq, void *opaque, int n, int level)
 {
     CPUState *env = first_cpu;
 
-    DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
+    DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", n);
     if (env->apic_state) {
         while (env) {
             if (apic_accept_pic_intr(env))
@@ -378,7 +378,8 @@  void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
     rtc_set_memory(s, 0x39, val);
 }
 
-static void handle_a20_line_change(void *opaque, int irq, int level)
+static void handle_a20_line_change(qemu_irq irq, void *opaque, int n,
+                                   int level)
 {
     CPUState *cpu = opaque;
 
@@ -750,7 +751,7 @@  int cpu_is_bsp(CPUState *env)
 
 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
    BIOS will read it and start S3 resume at POST Entry */
-void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
+void pc_cmos_set_s3_resume(qemu_irq irq, void *opaque, int n, int level)
 {
     ISADevice *s = opaque;
 
@@ -759,7 +760,7 @@  void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
     }
 }
 
-void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
+void pc_acpi_smi_interrupt(qemu_irq irq, void *opaque, int n, int level)
 {
     CPUState *s = opaque;
 
@@ -927,7 +928,7 @@  void pc_vga_init(PCIBus *pci_bus)
     }
 }
 
-static void cpu_request_exit(void *opaque, int irq, int level)
+static void cpu_request_exit(qemu_irq irq, void *opaque, int n, int level)
 {
     CPUState *env = cpu_single_env;
 
diff --git a/hw/pc.h b/hw/pc.h
index 0e52933..82b902f 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -29,8 +29,6 @@  ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq
 
 typedef struct PicState2 PicState2;
 extern PicState2 *isa_pic;
-void pic_set_irq(int irq, int level);
-void pic_set_irq_new(void *opaque, int irq, int level);
 qemu_irq *i8259_init(qemu_irq parent_irq);
 int pic_read_irq(PicState2 *s);
 void pic_update_irq(PicState2 *s);
@@ -44,7 +42,7 @@  typedef struct isa_irq_state {
     qemu_irq *ioapic;
 } IsaIrqState;
 
-void isa_irq_handler(void *opaque, int n, int level);
+void isa_irq_handler(qemu_irq irq, void *opaque, int n, int level);
 
 /* i8254.c */
 
@@ -82,8 +80,8 @@  void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
 extern int fd_bootchk;
 
 void pc_register_ferr_irq(qemu_irq irq);
-void pc_cmos_set_s3_resume(void *opaque, int irq, int level);
-void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
+void pc_cmos_set_s3_resume(qemu_irq irq, void *opaque, int n, int level);
+void pc_acpi_smi_interrupt(qemu_irq irq, void *opaque, int n, int level);
 
 void pc_cpus_init(const char *cpu_model);
 void pc_memory_init(ram_addr_t ram_size,
diff --git a/hw/pci.c b/hw/pci.c
index cbbd1dd..edca65a 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -72,7 +72,7 @@  static struct BusInfo pci_bus_info = {
 };
 
 static void pci_update_mappings(PCIDevice *d);
-static void pci_set_irq(void *opaque, int irq_num, int level);
+static void pci_set_irq(qemu_irq irq, void *opaque, int irq_num, int level);
 static int pci_add_option_rom(PCIDevice *pdev);
 
 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
@@ -1037,7 +1037,7 @@  void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 /* generic PCI irq support */
 
 /* 0 <= irq_num <= 3. level must be 0 or 1 */
-static void pci_set_irq(void *opaque, int irq_num, int level)
+static void pci_set_irq(qemu_irq irq, void *opaque, int irq_num, int level)
 {
     PCIDevice *pci_dev = opaque;
     int change;
diff --git a/hw/pl061.c b/hw/pl061.c
index 7b1b636..e9490bb 100644
--- a/hw/pl061.c
+++ b/hw/pl061.c
@@ -209,12 +209,12 @@  static void pl061_reset(pl061_state *s)
   s->cr = 0xff;
 }
 
-static void pl061_set_irq(void * opaque, int irq, int level)
+static void pl061_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     pl061_state *s = (pl061_state *)opaque;
     uint8_t mask;
 
-    mask = 1 << irq;
+    mask = 1 << n;
     if ((s->dir & mask) == 0) {
         s->data &= ~mask;
         if (level)
diff --git a/hw/pl190.c b/hw/pl190.c
index a4bc9c1..a00d86b 100644
--- a/hw/pl190.c
+++ b/hw/pl190.c
@@ -54,14 +54,14 @@  static void pl190_update(pl190_state *s)
     qemu_set_irq(s->fiq, set);
 }
 
-static void pl190_set_irq(void *opaque, int irq, int level)
+static void pl190_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     pl190_state *s = (pl190_state *)opaque;
 
     if (level)
-        s->level |= 1u << irq;
+        s->level |= 1u << n;
     else
-        s->level &= ~(1u << irq);
+        s->level &= ~(1u << n);
     pl190_update(s);
 }
 
diff --git a/hw/ppc.c b/hw/ppc.c
index 2a77eb9..2aef868 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -64,7 +64,7 @@  static void ppc_set_irq (CPUState *env, int n_IRQ, int level)
 }
 
 /* PowerPC 6xx / 7xx internal IRQ controller */
-static void ppc6xx_set_irq (void *opaque, int pin, int level)
+static void ppc6xx_set_irq (qemu_irq irq, void *opaque, int pin, int level)
 {
     CPUState *env = opaque;
     int cur_level;
@@ -154,7 +154,7 @@  void ppc6xx_irq_init (CPUState *env)
 
 #if defined(TARGET_PPC64)
 /* PowerPC 970 internal IRQ controller */
-static void ppc970_set_irq (void *opaque, int pin, int level)
+static void ppc970_set_irq (qemu_irq irq, void *opaque, int pin, int level)
 {
     CPUState *env = opaque;
     int cur_level;
@@ -238,7 +238,7 @@  void ppc970_irq_init (CPUState *env)
 #endif /* defined(TARGET_PPC64) */
 
 /* PowerPC 40x internal IRQ controller */
-static void ppc40x_set_irq (void *opaque, int pin, int level)
+static void ppc40x_set_irq (qemu_irq irq, void *opaque, int pin, int level)
 {
     CPUState *env = opaque;
     int cur_level;
@@ -316,7 +316,7 @@  void ppc40x_irq_init (CPUState *env)
 }
 
 /* PowerPC E500 internal IRQ controller */
-static void ppce500_set_irq (void *opaque, int pin, int level)
+static void ppce500_set_irq (qemu_irq irq, void *opaque, int pin, int level)
 {
     CPUState *env = opaque;
     int cur_level;
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index 37a3948..732b17d 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -147,7 +147,7 @@  static void ppcuic_trigger_irq (ppcuic_t *uic)
     }
 }
 
-static void ppcuic_set_irq (void *opaque, int irq_num, int level)
+static void ppcuic_set_irq (qemu_irq irq, void *opaque, int irq_num, int level)
 {
     ppcuic_t *uic;
     uint32_t mask, sr;
diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c
index 16c9950..fd1ca86 100644
--- a/hw/ppc_prep.c
+++ b/hw/ppc_prep.c
@@ -547,7 +547,7 @@  static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
 
 #define NVRAM_SIZE        0x2000
 
-static void cpu_request_exit(void *opaque, int irq, int level)
+static void cpu_request_exit(qemu_irq irq, void *opaque, int n, int level)
 {
     CPUState *env = cpu_single_env;
 
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index 9095386..aef4259 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -2019,7 +2019,7 @@  static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
     return s;
 }
 
-static void pxa2xx_reset(void *opaque, int line, int level)
+static void pxa2xx_reset(qemu_irq irq, void *opaque, int line, int level)
 {
     PXA2xxState *s = (PXA2xxState *) opaque;
 
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
index f354f4b..7a7e538 100644
--- a/hw/pxa2xx_gpio.c
+++ b/hw/pxa2xx_gpio.c
@@ -86,7 +86,7 @@  static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
     0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
 };
 
-static void pxa2xx_gpio_set(void *opaque, int line, int level)
+static void pxa2xx_gpio_set(qemu_irq irq, void *opaque, int line, int level)
 {
     PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
     int bank;
diff --git a/hw/pxa2xx_pcmcia.c b/hw/pxa2xx_pcmcia.c
index be1309f..0e46d9e 100644
--- a/hw/pxa2xx_pcmcia.c
+++ b/hw/pxa2xx_pcmcia.c
@@ -121,7 +121,8 @@  static CPUWriteMemoryFunc * const pxa2xx_pcmcia_io_writefn[] = {
     pxa2xx_pcmcia_io_write,
 };
 
-static void pxa2xx_pcmcia_set_irq(void *opaque, int line, int level)
+static void pxa2xx_pcmcia_set_irq(qemu_irq irq, void *opaque, int line,
+                                  int level)
 {
     PXA2xxPCMCIAState *s = (PXA2xxPCMCIAState *) opaque;
     if (!s->irq)
diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
index 0a98342..67163ce 100644
--- a/hw/pxa2xx_pic.c
+++ b/hw/pxa2xx_pic.c
@@ -67,16 +67,16 @@  static void pxa2xx_pic_update(void *opaque)
 
 /* Note: Here level means state of the signal on a pin, not
  * IRQ/FIQ distinction as in PXA Developer Manual.  */
-static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
+static void pxa2xx_pic_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     PXA2xxPICState *s = (PXA2xxPICState *) opaque;
-    int int_set = (irq >= 32);
-    irq &= 31;
+    int int_set = (n >= 32);
+    n &= 31;
 
     if (level)
-        s->int_pending[int_set] |= 1 << irq;
+        s->int_pending[int_set] |= 1 << n;
     else
-        s->int_pending[int_set] &= ~(1 << irq);
+        s->int_pending[int_set] &= ~(1 << n);
 
     pxa2xx_pic_update(opaque);
 }
diff --git a/hw/r2d.c b/hw/r2d.c
index 38c4f6a..eb8e6e0 100644
--- a/hw/r2d.c
+++ b/hw/r2d.c
@@ -114,7 +114,7 @@  static void update_irl(r2d_fpga_t *fpga)
     qemu_set_irq(fpga->irl, irl ^ 15);
 }
 
-static void r2d_fpga_irq_set(void *opaque, int n, int level)
+static void r2d_fpga_irq_set(qemu_irq irq, void *opaque, int n, int level)
 {
     r2d_fpga_t *fpga = opaque;
     if (level)
diff --git a/hw/rc4030.c b/hw/rc4030.c
index 2a8233a..09260de 100644
--- a/hw/rc4030.c
+++ b/hw/rc4030.c
@@ -459,14 +459,15 @@  static void update_jazz_irq(rc4030State *s)
         qemu_irq_lower(s->jazz_bus_irq);
 }
 
-static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
+static void rc4030_irq_jazz_request(qemu_irq irq, void *opaque, int n,
+                                    int level)
 {
     rc4030State *s = opaque;
 
     if (level) {
-        s->isr_jazz |= 1 << irq;
+        s->isr_jazz |= 1 << n;
     } else {
-        s->isr_jazz &= ~(1 << irq);
+        s->isr_jazz &= ~(1 << n);
     }
 
     update_jazz_irq(s);
diff --git a/hw/sbi.c b/hw/sbi.c
index c4adc09..0783efa 100644
--- a/hw/sbi.c
+++ b/hw/sbi.c
@@ -47,7 +47,7 @@  typedef struct SBIState {
 
 #define SBI_SIZE (SBI_NREGS * 4)
 
-static void sbi_set_irq(void *opaque, int irq, int level)
+static void sbi_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
 }
 
diff --git a/hw/sh_intc.c b/hw/sh_intc.c
index da36d32..8bb1b07 100644
--- a/hw/sh_intc.c
+++ b/hw/sh_intc.c
@@ -71,7 +71,7 @@  void sh_intc_toggle_source(struct intc_source *source,
   }
 }
 
-static void sh_intc_set_irq (void *opaque, int n, int level)
+static void sh_intc_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
   struct intc_desc *desc = opaque;
   struct intc_source *source = &(desc->sources[n]);
@@ -467,7 +467,7 @@  int sh_intc_init(struct intc_desc *desc,
 
 /* Assert level <n> IRL interrupt. 
    0:deassert. 1:lowest priority,... 15:highest priority. */
-void sh_intc_set_irl(void *opaque, int n, int level)
+void sh_intc_set_irl(qemu_irq irq, void *opaque, int n, int level)
 {
     struct intc_source *s = opaque;
     int i, irl = level ^ 15;
diff --git a/hw/sh_intc.h b/hw/sh_intc.h
index c117d6f..2dbe391 100644
--- a/hw/sh_intc.h
+++ b/hw/sh_intc.h
@@ -75,6 +75,6 @@  int sh_intc_init(struct intc_desc *desc,
 		 struct intc_prio_reg *prio_regs,
 		 int nr_prio_regs);
 
-void sh_intc_set_irl(void *opaque, int n, int level);
+void sh_intc_set_irl(qemu_irq irq, void *opaque, int n, int level);
 
 #endif /* __SH_INTC_H__ */
diff --git a/hw/sharpsl.h b/hw/sharpsl.h
index c5ccf79..ca7e001 100644
--- a/hw/sharpsl.h
+++ b/hw/sharpsl.h
@@ -13,7 +13,6 @@ 
 typedef struct ScoopInfo ScoopInfo;
 ScoopInfo *scoop_init(PXA2xxState *cpu,
                 int instance, target_phys_addr_t target_base);
-void scoop_gpio_set(void *opaque, int line, int level);
 qemu_irq *scoop_gpio_in_get(ScoopInfo *s);
 void scoop_gpio_out_set(ScoopInfo *s, int line,
                 qemu_irq handler);
diff --git a/hw/slavio_intctl.c b/hw/slavio_intctl.c
index b76d3ac..174ebca 100644
--- a/hw/slavio_intctl.c
+++ b/hw/slavio_intctl.c
@@ -317,14 +317,14 @@  static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
  * "irq" here is the bit number in the system interrupt register to
  * separate serial and keyboard interrupts sharing a level.
  */
-static void slavio_set_irq(void *opaque, int irq, int level)
+static void slavio_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     SLAVIO_INTCTLState *s = opaque;
-    uint32_t mask = 1 << irq;
-    uint32_t pil = intbit_to_level[irq];
+    uint32_t mask = 1 << n;
+    uint32_t pil = intbit_to_level[n];
     unsigned int i;
 
-    DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
+    DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, n, pil,
             level);
     if (pil > 0) {
         if (level) {
@@ -364,12 +364,12 @@  static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
     slavio_check_interrupts(s, 1);
 }
 
-static void slavio_set_irq_all(void *opaque, int irq, int level)
+static void slavio_set_irq_all(qemu_irq irq, void *opaque, int n, int level)
 {
-    if (irq < 32) {
-        slavio_set_irq(opaque, irq, level);
+    if (n < 32) {
+        slavio_set_irq(irq, opaque, n, level);
     } else {
-        slavio_set_timer_irq_cpu(opaque, irq - 32, level);
+        slavio_set_timer_irq_cpu(opaque, n - 32, level);
     }
 }
 
diff --git a/hw/slavio_misc.c b/hw/slavio_misc.c
index 5ae628d..337c2e1 100644
--- a/hw/slavio_misc.c
+++ b/hw/slavio_misc.c
@@ -95,7 +95,8 @@  static void slavio_misc_reset(DeviceState *d)
     s->config = s->aux1 = s->aux2 = s->mctrl = 0;
 }
 
-static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
+static void slavio_set_power_fail(qemu_irq irq, void *opaque, int n,
+                                  int power_failing)
 {
     MiscState *s = opaque;
 
diff --git a/hw/sparc32_dma.c b/hw/sparc32_dma.c
index b521707..1e629da 100644
--- a/hw/sparc32_dma.c
+++ b/hw/sparc32_dma.c
@@ -127,7 +127,7 @@  void ledma_memory_write(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static void dma_set_irq(void *opaque, int irq, int level)
+static void dma_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     DMAState *s = opaque;
     if (level) {
diff --git a/hw/spitz.c b/hw/spitz.c
index 4f82e24..010316c 100644
--- a/hw/spitz.c
+++ b/hw/spitz.c
@@ -253,7 +253,8 @@  static void spitz_keyboard_sense_update(SpitzKeyboardState *s)
     s->sense_state = sense;
 }
 
-static void spitz_keyboard_strobe(void *opaque, int line, int level)
+static void spitz_keyboard_strobe(qemu_irq irq, void *opaque, int line,
+                                  int level)
 {
     SpitzKeyboardState *s = (SpitzKeyboardState *) opaque;
 
@@ -649,7 +650,7 @@  static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
     return 0;
 }
 
-static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
+static void corgi_ssp_gpio_cs(qemu_irq irq, void *opaque, int line, int level)
 {
     CorgiSSPState *s = (CorgiSSPState *)opaque;
     assert(line >= 0 && line < 3);
@@ -769,7 +770,7 @@  static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
 #define SPITZ_GPIO_WM	5
 
 #ifdef HAS_AUDIO
-static void spitz_wm8750_addr(void *opaque, int line, int level)
+static void spitz_wm8750_addr(qemu_irq irq, void *opaque, int line, int level)
 {
     i2c_slave *wm = (i2c_slave *) opaque;
     if (level)
@@ -790,7 +791,7 @@  static void spitz_i2c_setup(PXA2xxState *cpu)
     /* Attach a WM8750 to the bus */
     wm = i2c_create_slave(bus, "wm8750", 0);
 
-    spitz_wm8750_addr(wm, 0, 0);
+    spitz_wm8750_addr(NULL, wm, 0, 0);
     pxa2xx_gpio_out_set(cpu->gpio, SPITZ_GPIO_WM,
                     qemu_allocate_irqs(spitz_wm8750_addr, wm, 1)[0]);
     /* .. and to the sound interface.  */
@@ -810,7 +811,7 @@  static void spitz_akita_i2c_setup(PXA2xxState *cpu)
 
 /* Other peripherals */
 
-static void spitz_out_switch(void *opaque, int line, int level)
+static void spitz_out_switch(qemu_irq irq, void *opaque, int line, int level)
 {
     switch (line) {
     case 0:
@@ -882,7 +883,8 @@  static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
 
 static int spitz_hsync;
 
-static void spitz_lcd_hsync_handler(void *opaque, int line, int level)
+static void spitz_lcd_hsync_handler(qemu_irq irq, void *opaque, int line,
+                                    int level)
 {
     PXA2xxState *cpu = (PXA2xxState *) opaque;
     qemu_set_irq(pxa2xx_gpio_in_get(cpu->gpio)[SPITZ_GPIO_HSYNC], spitz_hsync);
diff --git a/hw/ssd0323.c b/hw/ssd0323.c
index b632825..140f661 100644
--- a/hw/ssd0323.c
+++ b/hw/ssd0323.c
@@ -268,7 +268,7 @@  static void ssd0323_invalidate_display(void * opaque)
 }
 
 /* Command/data input.  */
-static void ssd0323_cd(void *opaque, int n, int level)
+static void ssd0323_cd(qemu_irq irq, void *opaque, int n, int level)
 {
     ssd0323_state *s = (ssd0323_state *)opaque;
     DPRINTF("%s mode\n", level ? "Data" : "Command");
diff --git a/hw/stellaris.c b/hw/stellaris.c
index 5755f8a..45a11dd 100644
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -974,7 +974,8 @@  static void stellaris_adc_update(stellaris_adc_state *s)
     }
 }
 
-static void stellaris_adc_trigger(void *opaque, int irq, int level)
+static void stellaris_adc_trigger(qemu_irq irq, void *opaque, int line,
+                                  int level)
 {
     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
     int n;
@@ -1215,7 +1216,8 @@  typedef struct {
     SSIBus *bus[2];
 } stellaris_ssi_bus_state;
 
-static void stellaris_ssi_bus_select(void *opaque, int irq, int level)
+static void stellaris_ssi_bus_select(qemu_irq irq, void *opaque, int line,
+                                     int level)
 {
     stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque;
 
diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c
index 7d7542d..6c6f5bb 100644
--- a/hw/sun4c_intctl.c
+++ b/hw/sun4c_intctl.c
@@ -148,13 +148,13 @@  static void sun4c_check_interrupts(void *opaque)
 /*
  * "irq" here is the bit number in the system interrupt register
  */
-static void sun4c_set_irq(void *opaque, int irq, int level)
+static void sun4c_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     Sun4c_INTCTLState *s = opaque;
-    uint32_t mask = 1 << irq;
-    uint32_t pil = intbit_to_level[irq];
+    uint32_t mask = 1 << n;
+    uint32_t pil = intbit_to_level[n];
 
-    DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
+    DPRINTF("Set irq %d -> pil %d level %d\n", n, pil,
             level);
     if (pil > 0) {
         if (level) {
diff --git a/hw/sun4m.c b/hw/sun4m.c
index e4ca8f3..bbfa4f4 100644
--- a/hw/sun4m.c
+++ b/hw/sun4m.c
@@ -255,23 +255,23 @@  void cpu_check_irqs(CPUState *env)
     }
 }
 
-static void cpu_set_irq(void *opaque, int irq, int level)
+static void cpu_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     CPUState *env = opaque;
 
     if (level) {
-        DPRINTF("Raise CPU IRQ %d\n", irq);
+        DPRINTF("Raise CPU IRQ %d\n", n);
         env->halted = 0;
-        env->pil_in |= 1 << irq;
+        env->pil_in |= 1 << n;
         cpu_check_irqs(env);
     } else {
-        DPRINTF("Lower CPU IRQ %d\n", irq);
-        env->pil_in &= ~(1 << irq);
+        DPRINTF("Lower CPU IRQ %d\n", n);
+        env->pil_in &= ~(1 << n);
         cpu_check_irqs(env);
     }
 }
 
-static void dummy_cpu_set_irq(void *opaque, int irq, int level)
+static void dummy_cpu_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
 }
 
@@ -291,7 +291,7 @@  static void secondary_cpu_reset(void *opaque)
     env->halted = 1;
 }
 
-static void cpu_halt_signal(void *opaque, int irq, int level)
+static void cpu_halt_signal(qemu_irq irq, void *opaque, int n, int level)
 {
     if (level && cpu_single_env)
         cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 40b5f1f..0df1051 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -299,18 +299,18 @@  static void cpu_kick_irq(CPUState *env)
     cpu_check_irqs(env);
 }
 
-static void cpu_set_irq(void *opaque, int irq, int level)
+static void cpu_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     CPUState *env = opaque;
 
     if (level) {
-        CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
+        CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", n);
         env->halted = 0;
-        env->pil_in |= 1 << irq;
+        env->pil_in |= 1 << n;
         cpu_check_irqs(env);
     } else {
-        CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
-        env->pil_in &= ~(1 << irq);
+        CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", n);
+        env->pil_in &= ~(1 << n);
         cpu_check_irqs(env);
     }
 }
@@ -532,7 +532,7 @@  static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
     }
 }
 
-static void dummy_isa_irq_handler(void *opaque, int n, int level)
+static void dummy_isa_irq_handler(qemu_irq irq, void *opaque, int n, int level)
 {
 }
 
diff --git a/hw/syborg_interrupt.c b/hw/syborg_interrupt.c
index f3a1767..d108712 100644
--- a/hw/syborg_interrupt.c
+++ b/hw/syborg_interrupt.c
@@ -67,15 +67,15 @@  static void syborg_int_update(SyborgIntState *s)
     qemu_set_irq(s->parent_irq, s->pending_count > 0);
 }
 
-static void syborg_int_set_irq(void *opaque, int irq, int level)
+static void syborg_int_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     SyborgIntState *s = (SyborgIntState *)opaque;
 
-    if (s->flags[irq].level == level)
+    if (s->flags[n].level == level)
         return;
 
-    s->flags[irq].level = level;
-    if (s->flags[irq].enabled) {
+    s->flags[n].level = level;
+    if (s->flags[n].enabled) {
         if (level)
             s->pending_count++;
         else
diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c
index e0c5e5f..ff8165a 100644
--- a/hw/tc6393xb.c
+++ b/hw/tc6393xb.c
@@ -135,7 +135,7 @@  qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
     return s->gpio_in;
 }
 
-static void tc6393xb_gpio_set(void *opaque, int line, int level)
+static void tc6393xb_gpio_set(qemu_irq irq, void *opaque, int line, int level)
 {
 //    TC6393xbState *s = opaque;
 
@@ -178,14 +178,15 @@  qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
     return s->l3v;
 }
 
-static void tc6393xb_l3v(void *opaque, int line, int level)
+static void tc6393xb_l3v(qemu_irq irq, void *opaque, int line, int level)
 {
     TC6393xbState *s = opaque;
     s->blank = !level;
     fprintf(stderr, "L3V: %d\n", level);
 }
 
-static void tc6393xb_sub_irq(void *opaque, int line, int level) {
+static void tc6393xb_sub_irq(qemu_irq irq, void *opaque, int line, int level)
+{
     TC6393xbState *s = opaque;
     uint8_t isr = s->scr.ISR;
     if (level)
diff --git a/hw/tosa.c b/hw/tosa.c
index fbe8d8c..2a1954b 100644
--- a/hw/tosa.c
+++ b/hw/tosa.c
@@ -62,7 +62,7 @@  static void tosa_microdrive_attach(PXA2xxState *cpu)
     }
 }
 
-static void tosa_out_switch(void *opaque, int line, int level)
+static void tosa_out_switch(qemu_irq irq, void *opaque, int line, int level)
 {
     switch (line) {
         case 0:
diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index 4864be5..ab28667 100644
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -678,7 +678,8 @@  static void tusb_power_tick(void *opaque)
     }
 }
 
-static void tusb_musb_core_intr(void *opaque, int source, int level)
+static void tusb_musb_core_intr(qemu_irq irq, void *opaque, int source,
+                                int level)
 {
     TUSBState *s = (TUSBState *) opaque;
     uint16_t otg_status = s->otg_status;
diff --git a/hw/twl92230.c b/hw/twl92230.c
index e61f17f..3ab8dfd 100644
--- a/hw/twl92230.c
+++ b/hw/twl92230.c
@@ -183,7 +183,7 @@  static void menelaus_reset(i2c_slave *i2c)
     menelaus_update(s);
 }
 
-static void menelaus_gpio_set(void *opaque, int line, int level)
+static void menelaus_gpio_set(qemu_irq irq, void *opaque, int line, int level)
 {
     MenelausState *s = (MenelausState *) opaque;
 
@@ -192,7 +192,8 @@  static void menelaus_gpio_set(void *opaque, int line, int level)
     s->inputs |= level << line;
 }
 
-static void menelaus_pwrbtn_set(void *opaque, int line, int level)
+static void menelaus_pwrbtn_set(qemu_irq irq, void *opaque, int line,
+                                int level)
 {
     MenelausState *s = (MenelausState *) opaque;
 
diff --git a/hw/versatilepb.c b/hw/versatilepb.c
index 391f5b8..49a780a 100644
--- a/hw/versatilepb.c
+++ b/hw/versatilepb.c
@@ -50,15 +50,15 @@  static void vpb_sic_update_pic(vpb_sic_state *s)
     }
 }
 
-static void vpb_sic_set_irq(void *opaque, int irq, int level)
+static void vpb_sic_set_irq(qemu_irq irq, void *opaque, int n, int level)
 {
     vpb_sic_state *s = (vpb_sic_state *)opaque;
     if (level)
-        s->level |= 1u << irq;
+        s->level |= 1u << n;
     else
-        s->level &= ~(1u << irq);
-    if (s->pic_enable & (1u << irq))
-        qemu_set_irq(s->parent[irq], level);
+        s->level &= ~(1u << n);
+    if (s->pic_enable & (1u << n))
+        qemu_set_irq(s->parent[n], level);
     vpb_sic_update(s);
 }
 
diff --git a/hw/xilinx_intc.c b/hw/xilinx_intc.c
index 8ef6474..20b0267 100644
--- a/hw/xilinx_intc.c
+++ b/hw/xilinx_intc.c
@@ -126,7 +126,7 @@  static CPUWriteMemoryFunc * const pic_write[] = {
     &pic_writel,
 };
 
-static void irq_handler(void *opaque, int irq, int level)
+static void irq_handler(qemu_irq irq, void *opaque, int n, int level)
 {
     struct xlx_pic *p = opaque;
 
@@ -138,9 +138,9 @@  static void irq_handler(void *opaque, int irq, int level)
     /* Update source flops. Don't clear unless level triggered.
        Edge triggered interrupts only go away when explicitely acked to
        the interrupt controller.  */
-    if (!(p->c_kind_of_intr & (1 << irq)) || level) {
-        p->regs[R_ISR] &= ~(1 << irq);
-        p->regs[R_ISR] |= (level << irq);
+    if (!(p->c_kind_of_intr & (1 << n)) || level) {
+        p->regs[R_ISR] &= ~(1 << n);
+        p->regs[R_ISR] |= (level << n);
     }
     update_irq(p);
 }
diff --git a/hw/zaurus.c b/hw/zaurus.c
index db6ba75..94c4ad7 100644
--- a/hw/zaurus.c
+++ b/hw/zaurus.c
@@ -153,7 +153,7 @@  static CPUWriteMemoryFunc * const scoop_writefn[] = {
     scoop_writeb,
 };
 
-void scoop_gpio_set(void *opaque, int line, int level)
+static void scoop_gpio_set(qemu_irq irq, void *opaque, int line, int level)
 {
     ScoopInfo *s = (ScoopInfo *) opaque;