| Message ID | 1448361929-41460-5-git-send-email-yao.yuan@freescale.com |
|---|---|
| State | Superseded |
| Delegated to: | York Sun |
| Headers | show |
Hi Yuan On 24/11/15 05:45 AM, Yuan Yao wrote: > Erratum number: ERR008514 > EDDRTQCFG Registers are Integration Strap values which controls > performance parameters for DDR Controller. > > The bit 25 is used to disable priorities within DDR since DDR > are connected backwards on Rev2.0 silicon for LS1021A. > > Signed-off-by: Yuan Yao <yao.yuan@freescale.com> > --- > arch/arm/cpu/armv7/ls102xa/soc.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c > index b15cd60..98d4acd 100644 > --- a/arch/arm/cpu/armv7/ls102xa/soc.c > +++ b/arch/arm/cpu/armv7/ls102xa/soc.c > @@ -25,7 +25,7 @@ int arch_soc_init(void) > { > struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; > struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; > - unsigned int major; > + unsigned int major, reg; > > #ifdef CONFIG_FSL_QSPI > out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); > @@ -86,5 +86,16 @@ int arch_soc_init(void) > */ > out_be32(&scfg->eddrtqcfg, 0x63b20002); > > + /* > + * EDDRTQCFG Registers are Integration Strap values which controls > + * performance parameters for DDR Controller. > + * The bit 25 is used for disable priorities within DDR. > + * This is a workaround because of the DDR are connected backwards > + * on Rev2.0. Would this cause any problem with Rev1.0 ? If it does, should we check the revision here. Regards Sinan Akman > + */ > + reg = in_be32(&scfg->eddrtqcfg); > + reg |= 1 << 6; > + out_be32(&scfg->eddrtqcfg, reg); > + > return 0; > } >
Hi Sinan Akman, Thanks for your review. There should not cause any problem with Rev1.0. The workaround should also apply to rev1.0. Best Regards, Yuan Yao > -----Original Message----- > From: Sinan Akman [mailto:sinan@writeme.com] > Sent: Wednesday, November 25, 2015 12:10 AM > To: Yuan Yao-B46683 <yao.yuan@freescale.com>; Sun York-R58495 > <yorksun@freescale.com> > Cc: u-boot@lists.denx.de; Wang Huan-B18965 <alison.wang@freescale.com> > Subject: Re: [U-Boot] [PATCH 5/6] LS102XA:workaround:disable priorities > within DDR > > > Hi Yuan > > On 24/11/15 05:45 AM, Yuan Yao wrote: > > Erratum number: ERR008514 > > EDDRTQCFG Registers are Integration Strap values which controls > > performance parameters for DDR Controller. > > > > The bit 25 is used to disable priorities within DDR since DDR are > > connected backwards on Rev2.0 silicon for LS1021A. > > > > Signed-off-by: Yuan Yao <yao.yuan@freescale.com> > > --- > > arch/arm/cpu/armv7/ls102xa/soc.c | 13 ++++++++++++- > > 1 file changed, 12 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c > > b/arch/arm/cpu/armv7/ls102xa/soc.c > > index b15cd60..98d4acd 100644 > > --- a/arch/arm/cpu/armv7/ls102xa/soc.c > > +++ b/arch/arm/cpu/armv7/ls102xa/soc.c > > @@ -25,7 +25,7 @@ int arch_soc_init(void) > > { > > struct ccsr_scfg *scfg = (struct ccsr_scfg > *)CONFIG_SYS_FSL_SCFG_ADDR; > > struct ccsr_cci400 *cci = (struct ccsr_cci400 > *)CONFIG_SYS_CCI400_ADDR; > > - unsigned int major; > > + unsigned int major, reg; > > > > #ifdef CONFIG_FSL_QSPI > > out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); @@ -86,5 +86,16 @@ > int > > arch_soc_init(void) > > */ > > out_be32(&scfg->eddrtqcfg, 0x63b20002); > > > > + /* > > + * EDDRTQCFG Registers are Integration Strap values which controls > > + * performance parameters for DDR Controller. > > + * The bit 25 is used for disable priorities within DDR. > > + * This is a workaround because of the DDR are connected backwards > > + * on Rev2.0. > > Would this cause any problem with Rev1.0 ? > If it does, should we check the revision here. > > Regards > Sinan Akman > > > + */ > > + reg = in_be32(&scfg->eddrtqcfg); > > + reg |= 1 << 6; > > + out_be32(&scfg->eddrtqcfg, reg); > > + > > return 0; > > } > >
Yuan, On 11/25/2015 01:14 AM, Yuan Yao-B46683 wrote: > Hi Sinan Akman, > > Thanks for your review. > There should not cause any problem with Rev1.0. > The workaround should also apply to rev1.0. Please squash your patch 4 & 5 and update your comment and commit message. The erratum document changes from writing 0x63b20002 to 0x63b20042 for LS102x rev 1.0 and rev 2.0. York
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index b15cd60..98d4acd 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -25,7 +25,7 @@ int arch_soc_init(void) { struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; - unsigned int major; + unsigned int major, reg; #ifdef CONFIG_FSL_QSPI out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); @@ -86,5 +86,16 @@ int arch_soc_init(void) */ out_be32(&scfg->eddrtqcfg, 0x63b20002); + /* + * EDDRTQCFG Registers are Integration Strap values which controls + * performance parameters for DDR Controller. + * The bit 25 is used for disable priorities within DDR. + * This is a workaround because of the DDR are connected backwards + * on Rev2.0. + */ + reg = in_be32(&scfg->eddrtqcfg); + reg |= 1 << 6; + out_be32(&scfg->eddrtqcfg, reg); + return 0; }
Erratum number: ERR008514 EDDRTQCFG Registers are Integration Strap values which controls performance parameters for DDR Controller. The bit 25 is used to disable priorities within DDR since DDR are connected backwards on Rev2.0 silicon for LS1021A. Signed-off-by: Yuan Yao <yao.yuan@freescale.com> --- arch/arm/cpu/armv7/ls102xa/soc.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)