From patchwork Mon Nov 23 10:02:25 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Whitcroft X-Patchwork-Id: 547431 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from huckleberry.canonical.com (huckleberry.canonical.com [91.189.94.19]) by ozlabs.org (Postfix) with ESMTP id 176611402B6; Mon, 23 Nov 2015 21:02:38 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=huckleberry.canonical.com) by huckleberry.canonical.com with esmtp (Exim 4.76) (envelope-from ) id 1a0nx9-0006hj-RK; Mon, 23 Nov 2015 10:02:31 +0000 Received: from mail-wm0-f41.google.com ([74.125.82.41]) by huckleberry.canonical.com with esmtp (Exim 4.76) (envelope-from ) id 1a0nx5-0006hU-3k for kernel-team@lists.ubuntu.com; Mon, 23 Nov 2015 10:02:27 +0000 Received: by wmvv187 with SMTP id v187so152395554wmv.1 for ; Mon, 23 Nov 2015 02:02:27 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-type:content-disposition:in-reply-to :user-agent; bh=7iuusvVx3AB2BxrBWSufbs9VkiFmd6rCyXqT/6an6wI=; b=QKzLLyIPgZCzMEnd19kdlAvgdr4h9ESPbkUXikUFH0A2EZGM9AtUaNNgARYnd9CNCm BjySJ8FpjnL269QV3oI3bSOPApV9ate5Qv2yxaZYAwzhCGhVoBL87WHPrEhyWRRt3Pri W1crfxeGn+zdvkRuuZJxXtVl6yrAonvtQiclJ0g12PIAjkLlKV7icy+p00hbsi4MpSlG i7uuP4Elv6JH4t/1uvxAZzGggpzm7VDdQ+TNTieQ9A3qv+VTdabkjB0ydexP2qBKf/uq BkhhRDwq0IZyXjUXut+GO51ZUJALhob85vJ/J8ApDJBuWoLn6O0C24EnN8BdBkbpelyb 6smA== X-Gm-Message-State: ALoCoQm0/fbeSFf/pZrn701gdudJgd/4bsxocUvwAHnbxBKrq9vGnjXzOeELFHMaMKm5fTjByc71 X-Received: by 10.28.221.134 with SMTP id u128mr14649014wmg.70.1448272946848; Mon, 23 Nov 2015 02:02:26 -0800 (PST) Received: from localhost ([2001:470:6973:2:484b:35a4:90eb:3439]) by smtp.gmail.com with ESMTPSA id b84sm12356500wmh.15.2015.11.23.02.02.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 23 Nov 2015 02:02:25 -0800 (PST) Date: Mon, 23 Nov 2015 10:02:25 +0000 From: Andy Whitcroft To: "Zhang, Xiong Y" Subject: Re: [SRU][Precise][Trusty][Vivid][Wily]xhci: Workaround to get Intel xHCI reset working more reliably Message-ID: <20151123100225.GA17631@bark> References: <8082FF9BCB2B054996454E47167FF4EC0B0EF767@SHSMSX104.ccr.corp.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <8082FF9BCB2B054996454E47167FF4EC0B0EF767@SHSMSX104.ccr.corp.intel.com> User-Agent: Mutt/1.5.23 (2014-03-12) Cc: "kernel-team@lists.ubuntu.com" X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.14 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kernel-team-bounces@lists.ubuntu.com Sender: kernel-team-bounces@lists.ubuntu.com Commit in full: commit a5964396190d0c40dd549c23848c282fffa5d1f2 Author: Rajmohan Mani Date: Wed Nov 18 10:48:20 2015 +0200 xhci: Workaround to get Intel xHCI reset working more reliably Existing Intel xHCI controllers require a delay of 1 mS, after setting the CMD_RESET bit in command register, before accessing any HC registers. This allows the HC to complete the reset operation and be ready for HC register access. Without this delay, the subsequent HC register access, may result in a system hang, very rarely. Verified CherryView / Braswell platforms go through over 5000 warm reboot cycles (which was not possible without this patch), without any xHCI reset hang. Signed-off-by: Rajmohan Mani Tested-by: Joe Lawrence Cc: stable Signed-off-by: Mathias Nyman Signed-off-by: Greg Kroah-Hartman Acked-by: Andy Whitcroft diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 6e7dc6f..dfa44d3 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -175,6 +175,16 @@ int xhci_reset(struct xhci_hcd *xhci) command |= CMD_RESET; writel(command, &xhci->op_regs->command); + /* Existing Intel xHCI controllers require a delay of 1 mS, + * after setting the CMD_RESET bit, and before accessing any + * HC registers. This allows the HC to complete the + * reset operation and be ready for HC register access. + * Without this delay, the subsequent HC register access, + * may result in a system hang very rarely. + */ + if (xhci->quirks & XHCI_INTEL_HOST) + udelay(1000); + ret = xhci_handshake(&xhci->op_regs->command, CMD_RESET, 0, 10 * 1000 * 1000); if (ret)