From patchwork Fri Jun 4 19:14:38 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 54696 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 29EC7B7D2E for ; Sat, 5 Jun 2010 06:01:25 +1000 (EST) Received: from localhost ([127.0.0.1]:42291 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKd50-00033W-1i for incoming@patchwork.ozlabs.org; Fri, 04 Jun 2010 16:01:22 -0400 Received: from [140.186.70.92] (port=59159 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcON-00069r-St for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OKcOM-0002da-Mu for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:19 -0400 Received: from are.twiddle.net ([75.149.56.221]:54817) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OKcOM-0002dP-GV for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:17:18 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id A045EF7B; Fri, 4 Jun 2010 12:17:16 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o54JHFRP007309; Fri, 4 Jun 2010 12:17:15 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o54JHDJt007308; Fri, 4 Jun 2010 12:17:13 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 4 Jun 2010 12:14:38 -0700 Message-Id: <1275678883-7082-31-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1275678883-7082-1-git-send-email-rth@twiddle.net> References: <1275678883-7082-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 30/35] tcg-s390: Implement GUEST_BASE. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- configure | 2 ++ tcg/s390/tcg-target.c | 24 ++++++++++++++++++++++-- tcg/s390/tcg-target.h | 2 ++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 7f5b5b2..e80b820 100755 --- a/configure +++ b/configure @@ -699,10 +699,12 @@ case "$cpu" in s390) QEMU_CFLAGS="-m31 -march=z990 $QEMU_CFLAGS" LDFLAGS="-m31 $LDFLAGS" + host_guest_base="yes" ;; s390x) QEMU_CFLAGS="-m64 -march=z990 $QEMU_CFLAGS" LDFLAGS="-m64 $LDFLAGS" + host_guest_base="yes" ;; i386) QEMU_CFLAGS="-m32 $QEMU_CFLAGS" diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index ef1f69e..13c4de6 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -48,6 +48,16 @@ /* A scratch register that may be be used throughout the backend. */ #define TCG_TMP0 TCG_REG_R14 +#ifdef CONFIG_USE_GUEST_BASE +#define TCG_GUEST_BASE_REG TCG_REG_R13 +#else +#define TCG_GUEST_BASE_REG TCG_REG_R0 +#endif + +#ifndef GUEST_BASE +#define GUEST_BASE 0 +#endif + /* All of the following instructions are prefixed with their instruction format, and are defined as 8- or 16-bit quantities, even when the two @@ -1317,12 +1327,17 @@ static void tcg_finish_qemu_ldst(TCGContext* s, uint16_t *label2_ptr) static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg, TCGReg *index_reg, tcg_target_long *disp) { - *index_reg = TCG_REG_NONE; - *disp = 0; if (TARGET_LONG_BITS == 32) { tgen_ext32u(s, TCG_TMP0, *addr_reg); *addr_reg = TCG_TMP0; } + if (GUEST_BASE < 0x80000) { + *index_reg = TCG_REG_NONE; + *disp = GUEST_BASE; + } else { + *index_reg = TCG_GUEST_BASE_REG; + *disp = 0; + } } #endif /* CONFIG_SOFTMMU */ @@ -2061,6 +2076,11 @@ void tcg_target_qemu_prologue(TCGContext *s) /* aghi %r15,-160 (stack frame) */ tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -160); + if (GUEST_BASE >= 0x80000) { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); + } + /* br %r2 (go to TB) */ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R2); diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 9135c7a..390c587 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -83,6 +83,8 @@ typedef enum TCGReg { // #define TCG_TARGET_HAS_nand_i64 // #define TCG_TARGET_HAS_nor_i64 +#define TCG_TARGET_HAS_GUEST_BASE + /* used for function call generation */ #define TCG_REG_CALL_STACK TCG_REG_R15 #define TCG_TARGET_STACK_ALIGN 8