| Message ID | 20151120115223.GA4423@maggie |
|---|---|
| State | New |
| Headers | show |
On 11/20/2015 12:52 PM, Andreas Krebbel wrote: > +(define_insn "bswaphi2" > + [(set (match_operand:HI 0 "register_operand" "=d") > + (bswap:HI (match_operand:HI 1 "memory_operand" "RT")))] > + "TARGET_CPU_ZARCH" > + "lrvh\t%0,%1" > + [(set_attr "type" "load") > + (set_attr "op_type" "RXY") > + (set_attr "z10prop" "z10_super")]) Surely it's better to arrange so that you can use STRVH as well. And providing a fallback for the reg-reg case (e.g. LRVR+SRL). Although I suppose I don't see support for STRV in bswap32/64 either... r~
On 11/20/2015 01:23 PM, Richard Henderson wrote: > On 11/20/2015 12:52 PM, Andreas Krebbel wrote: >> +(define_insn "bswaphi2" >> + [(set (match_operand:HI 0 "register_operand" "=d") >> + (bswap:HI (match_operand:HI 1 "memory_operand" "RT")))] >> + "TARGET_CPU_ZARCH" >> + "lrvh\t%0,%1" >> + [(set_attr "type" "load") >> + (set_attr "op_type" "RXY") >> + (set_attr "z10prop" "z10_super")]) > > Surely it's better to arrange so that you can use STRVH as well. > And providing a fallback for the reg-reg case (e.g. LRVR+SRL). > > Although I suppose I don't see support for STRV in bswap32/64 either... Right, I totally forgot about the stores. I'll have a look. We even have a mem-mem variant (mvcin). But I found it rather difficult to use since the pattern would have to make sure that source and destination do not overlap. -Andreas-
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index ea65c74..280a772 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -10439,6 +10439,8 @@ ; Byte swap instructions ; +; FIXME: There is also mvcin but we cannot use it since src and target +; may overlap. (define_insn "bswap<mode>2" [(set (match_operand:GPR 0 "register_operand" "=d, d") (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))] @@ -10450,6 +10452,14 @@ (set_attr "op_type" "RRE,RXY") (set_attr "z10prop" "z10_super")]) +(define_insn "bswaphi2" + [(set (match_operand:HI 0 "register_operand" "=d") + (bswap:HI (match_operand:HI 1 "memory_operand" "RT")))] + "TARGET_CPU_ZARCH" + "lrvh\t%0,%1" + [(set_attr "type" "load") + (set_attr "op_type" "RXY") + (set_attr "z10prop" "z10_super")]) ; ; Population count instruction diff --git a/gcc/testsuite/gcc.target/s390/bswap-1.c b/gcc/testsuite/gcc.target/s390/bswap-1.c new file mode 100644 index 0000000..e1f113a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/bswap-1.c @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z900 -mzarch" } */ + +#include <stdint.h> + +uint64_t u64; +uint32_t u32; +uint16_t u16; + +uint64_t +foo64a (uint64_t a) +{ + return __builtin_bswap64 (a); +} +/* { dg-final { scan-assembler-times "lrvgr\t%r2,%r2" 1 { target lp64 } } } */ + +uint64_t +foo64b () +{ + return __builtin_bswap64 (u64); +} +/* { dg-final { scan-assembler-times "lrvg\t%r2,0\\(%r\[0-9\]*\\)" 1 { target lp64 } } } */ + +uint32_t +foo32 () +{ + return __builtin_bswap32 (u32); +} +/* { dg-final { scan-assembler-times "lrv\t%r2,0\\(%r\[0-9\]*\\)" 1 } } */ + +uint16_t +foo16 () +{ + return __builtin_bswap16 (u16); +} +/* { dg-final { scan-assembler-times "lrvh\t%r2,0\\(%r\[0-9\]*\\)" 1 } } */
Hi, the 16 bit bswap instruction support was missing in the back-end so far. Added with the attached patch. Bootstrapped on s390 and s390x. No regressions. Bye, -Andreas- gcc/testsuite/ChangeLog: 2015-11-20 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * gcc.target/s390/bswap-1.c: New test. gcc/ChangeLog: 2015-11-20 Andreas Krebbel <krebbel@linux.vnet.ibm.com> * config/s390/s390.md ("bswaphi2"): New pattern.