Patchwork [18/35] tcg-s390: Implement bswap operations.

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Submitter Richard Henderson
Date June 4, 2010, 7:14 p.m.
Message ID <1275678883-7082-19-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/54689/
State New
Headers show

Comments

Richard Henderson - June 4, 2010, 7:14 p.m.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/s390/tcg-target.c |   24 ++++++++++++++++++++++++
 tcg/s390/tcg-target.h |   10 +++++-----
 2 files changed, 29 insertions(+), 5 deletions(-)
Aurelien Jarno - June 12, 2010, 12:32 p.m.
On Fri, Jun 04, 2010 at 12:14:26PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/s390/tcg-target.c |   24 ++++++++++++++++++++++++
>  tcg/s390/tcg-target.h |   10 +++++-----
>  2 files changed, 29 insertions(+), 5 deletions(-)

This patch looks fine.

> diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
> index 42e3224..3a98ca3 100644
> --- a/tcg/s390/tcg-target.c
> +++ b/tcg/s390/tcg-target.c
> @@ -86,6 +86,8 @@ typedef enum S390Opcode {
>      RRE_LLGCR   = 0xb984,
>      RRE_LLGFR   = 0xb916,
>      RRE_LLGHR   = 0xb985,
> +    RRE_LRVR    = 0xb91f,
> +    RRE_LRVGR   = 0xb90f,
>      RRE_MSGR    = 0xb90c,
>      RRE_MSR     = 0xb252,
>      RRE_NGR     = 0xb980,
> @@ -1231,6 +1233,21 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
>          tgen_ext32u(s, args[0], args[1]);
>          break;
>  
> +    case INDEX_op_bswap16_i32:
> +    case INDEX_op_bswap16_i64:
> +        /* The TCG bswap definition requires bits 0-47 already be zero.
> +           Thus we don't need the G-type insns to implement bswap16_i64.  */
> +        tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
> +        tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16);
> +        break;
> +    case INDEX_op_bswap32_i32:
> +    case INDEX_op_bswap32_i64:
> +        tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
> +        break;
> +    case INDEX_op_bswap64_i64:
> +        tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
> +        break;
> +
>      case INDEX_op_br:
>          tgen_branch(s, S390_CC_ALWAYS, args[0]);
>          break;
> @@ -1353,6 +1370,9 @@ static const TCGTargetOpDef s390_op_defs[] = {
>      { INDEX_op_ext16s_i32, { "r", "r" } },
>      { INDEX_op_ext16u_i32, { "r", "r" } },
>  
> +    { INDEX_op_bswap16_i32, { "r", "r" } },
> +    { INDEX_op_bswap32_i32, { "r", "r" } },
> +
>      { INDEX_op_brcond_i32, { "r", "r" } },
>      { INDEX_op_setcond_i32, { "r", "r", "r" } },
>  
> @@ -1410,6 +1430,10 @@ static const TCGTargetOpDef s390_op_defs[] = {
>      { INDEX_op_ext32s_i64, { "r", "r" } },
>      { INDEX_op_ext32u_i64, { "r", "r" } },
>  
> +    { INDEX_op_bswap16_i64, { "r", "r" } },
> +    { INDEX_op_bswap32_i64, { "r", "r" } },
> +    { INDEX_op_bswap64_i64, { "r", "r" } },
> +
>      { INDEX_op_brcond_i64, { "r", "r" } },
>      { INDEX_op_setcond_i64, { "r", "r", "r" } },
>  #endif
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index 570c832..dcb9bc3 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -54,8 +54,8 @@ typedef enum TCGReg {
>  #define TCG_TARGET_HAS_ext16s_i32
>  #define TCG_TARGET_HAS_ext8u_i32
>  #define TCG_TARGET_HAS_ext16u_i32
> -// #define TCG_TARGET_HAS_bswap16_i32
> -// #define TCG_TARGET_HAS_bswap32_i32
> +#define TCG_TARGET_HAS_bswap16_i32
> +#define TCG_TARGET_HAS_bswap32_i32
>  // #define TCG_TARGET_HAS_not_i32
>  #define TCG_TARGET_HAS_neg_i32
>  // #define TCG_TARGET_HAS_andc_i32
> @@ -72,9 +72,9 @@ typedef enum TCGReg {
>  #define TCG_TARGET_HAS_ext8u_i64
>  #define TCG_TARGET_HAS_ext16u_i64
>  #define TCG_TARGET_HAS_ext32u_i64
> -// #define TCG_TARGET_HAS_bswap16_i64
> -// #define TCG_TARGET_HAS_bswap32_i64
> -// #define TCG_TARGET_HAS_bswap64_i64
> +#define TCG_TARGET_HAS_bswap16_i64
> +#define TCG_TARGET_HAS_bswap32_i64
> +#define TCG_TARGET_HAS_bswap64_i64
>  // #define TCG_TARGET_HAS_not_i64
>  #define TCG_TARGET_HAS_neg_i64
>  // #define TCG_TARGET_HAS_andc_i64
> -- 
> 1.7.0.1
> 
> 
>

Patch

diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index 42e3224..3a98ca3 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -86,6 +86,8 @@  typedef enum S390Opcode {
     RRE_LLGCR   = 0xb984,
     RRE_LLGFR   = 0xb916,
     RRE_LLGHR   = 0xb985,
+    RRE_LRVR    = 0xb91f,
+    RRE_LRVGR   = 0xb90f,
     RRE_MSGR    = 0xb90c,
     RRE_MSR     = 0xb252,
     RRE_NGR     = 0xb980,
@@ -1231,6 +1233,21 @@  static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tgen_ext32u(s, args[0], args[1]);
         break;
 
+    case INDEX_op_bswap16_i32:
+    case INDEX_op_bswap16_i64:
+        /* The TCG bswap definition requires bits 0-47 already be zero.
+           Thus we don't need the G-type insns to implement bswap16_i64.  */
+        tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
+        tcg_out_sh32(s, RS_SRL, args[0], TCG_REG_NONE, 16);
+        break;
+    case INDEX_op_bswap32_i32:
+    case INDEX_op_bswap32_i64:
+        tcg_out_insn(s, RRE, LRVR, args[0], args[1]);
+        break;
+    case INDEX_op_bswap64_i64:
+        tcg_out_insn(s, RRE, LRVGR, args[0], args[1]);
+        break;
+
     case INDEX_op_br:
         tgen_branch(s, S390_CC_ALWAYS, args[0]);
         break;
@@ -1353,6 +1370,9 @@  static const TCGTargetOpDef s390_op_defs[] = {
     { INDEX_op_ext16s_i32, { "r", "r" } },
     { INDEX_op_ext16u_i32, { "r", "r" } },
 
+    { INDEX_op_bswap16_i32, { "r", "r" } },
+    { INDEX_op_bswap32_i32, { "r", "r" } },
+
     { INDEX_op_brcond_i32, { "r", "r" } },
     { INDEX_op_setcond_i32, { "r", "r", "r" } },
 
@@ -1410,6 +1430,10 @@  static const TCGTargetOpDef s390_op_defs[] = {
     { INDEX_op_ext32s_i64, { "r", "r" } },
     { INDEX_op_ext32u_i64, { "r", "r" } },
 
+    { INDEX_op_bswap16_i64, { "r", "r" } },
+    { INDEX_op_bswap32_i64, { "r", "r" } },
+    { INDEX_op_bswap64_i64, { "r", "r" } },
+
     { INDEX_op_brcond_i64, { "r", "r" } },
     { INDEX_op_setcond_i64, { "r", "r", "r" } },
 #endif
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index 570c832..dcb9bc3 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -54,8 +54,8 @@  typedef enum TCGReg {
 #define TCG_TARGET_HAS_ext16s_i32
 #define TCG_TARGET_HAS_ext8u_i32
 #define TCG_TARGET_HAS_ext16u_i32
-// #define TCG_TARGET_HAS_bswap16_i32
-// #define TCG_TARGET_HAS_bswap32_i32
+#define TCG_TARGET_HAS_bswap16_i32
+#define TCG_TARGET_HAS_bswap32_i32
 // #define TCG_TARGET_HAS_not_i32
 #define TCG_TARGET_HAS_neg_i32
 // #define TCG_TARGET_HAS_andc_i32
@@ -72,9 +72,9 @@  typedef enum TCGReg {
 #define TCG_TARGET_HAS_ext8u_i64
 #define TCG_TARGET_HAS_ext16u_i64
 #define TCG_TARGET_HAS_ext32u_i64
-// #define TCG_TARGET_HAS_bswap16_i64
-// #define TCG_TARGET_HAS_bswap32_i64
-// #define TCG_TARGET_HAS_bswap64_i64
+#define TCG_TARGET_HAS_bswap16_i64
+#define TCG_TARGET_HAS_bswap32_i64
+#define TCG_TARGET_HAS_bswap64_i64
 // #define TCG_TARGET_HAS_not_i64
 #define TCG_TARGET_HAS_neg_i64
 // #define TCG_TARGET_HAS_andc_i64