From patchwork Fri Jun 4 19:14:20 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 54678 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CBD2FB6ED0 for ; Sat, 5 Jun 2010 05:31:01 +1000 (EST) Received: from localhost ([127.0.0.1]:38879 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcbZ-0005on-Bl for incoming@patchwork.ozlabs.org; Fri, 04 Jun 2010 15:30:57 -0400 Received: from [140.186.70.92] (port=37646 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKcN5-000564-R6 for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:16:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OKcN4-0002J3-E7 for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:15:59 -0400 Received: from are.twiddle.net ([75.149.56.221]:54771) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OKcN2-0002IX-VV for qemu-devel@nongnu.org; Fri, 04 Jun 2010 15:15:58 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id C3B2746D; Fri, 4 Jun 2010 12:15:53 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o54JFpbO007221; Fri, 4 Jun 2010 12:15:51 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o54JFlYT007211; Fri, 4 Jun 2010 12:15:47 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 4 Jun 2010 12:14:20 -0700 Message-Id: <1275678883-7082-13-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1275678883-7082-1-git-send-email-rth@twiddle.net> References: <1275678883-7082-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 12/35] tcg-s390: Define TCG_TMP0. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use a define for the temp register instead of hard-coding it. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 54 ++++++++++++++++++++++++++---------------------- 1 files changed, 29 insertions(+), 25 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 5b2134b..2b80c02 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -40,6 +40,10 @@ rather than TCG_REG_R0. */ #define TCG_REG_NONE 0 +/* A scratch register that may be be used throughout the backend. */ +#define TCG_TMP0 TCG_REG_R13 + + /* All of the following instructions are prefixed with their instruction format, and are defined as 8- or 16-bit quantities, even when the two halves of the 16-bit quantity may appear 32 bits apart in the insn. @@ -376,12 +380,12 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_insn(s, RI, IILH, ret, arg >> 16); } else { /* branch over constant and store its address in R13 */ - tcg_out_insn(s, RIL, BRASL, TCG_REG_R13, (6 + 8) >> 1); + tcg_out_insn(s, RIL, BRASL, TCG_TMP0, (6 + 8) >> 1); /* 64-bit constant */ tcg_out32(s, arg >> 32); tcg_out32(s, arg); /* load constant to ret */ - tcg_out_insn(s, RXY, LG, ret, TCG_REG_R13, 0, 0); + tcg_out_insn(s, RXY, LG, ret, TCG_TMP0, 0, 0); } } @@ -399,14 +403,14 @@ static void tcg_out_mem(TCGContext *s, S390Opcode opc_rx, S390Opcode opc_rxy, if (ofs < -0x80000 || ofs >= 0x80000) { /* Combine the low 16 bits of the offset with the actual load insn; the high 48 bits must come from an immediate load. */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, ofs & ~0xffff); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs & ~0xffff); ofs &= 0xffff; /* If we were already given an index register, add it in. */ if (index != TCG_REG_NONE) { - tcg_out_insn(s, RRE, AGR, TCG_REG_R13, index); + tcg_out_insn(s, RRE, AGR, TCG_TMP0, index); } - index = TCG_REG_R13; + index = TCG_TMP0; } if (opc_rx && ofs >= 0 && ofs < 0x1000) { @@ -482,8 +486,8 @@ static void tgen_gotoi(TCGContext *s, int cc, tcg_target_long dest) } else if (off == (int32_t)off) { tcg_out_insn(s, RIL, BRCL, cc, off); } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, dest); - tcg_out_insn(s, RR, BCR, cc, TCG_REG_R13); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, dest); + tcg_out_insn(s, RR, BCR, cc, TCG_TMP0); } } @@ -505,8 +509,8 @@ static void tgen_calli(TCGContext *s, tcg_target_long dest) if (off == (int32_t)off) { tcg_out_insn(s, RIL, BRASL, TCG_REG_R14, off); } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, dest); - tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_REG_R13); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, dest); + tcg_out_insn(s, RR, BASR, TCG_REG_R14, TCG_TMP0); } } @@ -538,22 +542,22 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, int data_reg, int addr_reg, tcg_out_sh64(s, RSY_SRLG, arg1, addr_reg, TCG_REG_NONE, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); - tcg_out_insn(s, RRE, NGR, arg0, TCG_REG_R13); + tcg_out_insn(s, RRE, NGR, arg0, TCG_TMP0); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); - tcg_out_insn(s, RRE, NGR, arg1, TCG_REG_R13); + tcg_out_insn(s, RRE, NGR, arg1, TCG_TMP0); if (is_store) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, offsetof(CPUState, tlb_table[mem_index][0].addr_write)); } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, offsetof(CPUState, tlb_table[mem_index][0].addr_read)); } - tcg_out_insn(s, RRE, AGR, arg1, TCG_REG_R13); + tcg_out_insn(s, RRE, AGR, arg1, TCG_TMP0); tcg_out_insn(s, RRE, AGR, arg1, TCG_AREG0); @@ -688,8 +692,8 @@ static void tcg_out_qemu_ld(TCGContext* s, const TCGArg* args, int opc) #else /* swapped unsigned halfword load with upper bits zeroed */ tcg_out_insn(s, RXY, LRVH, data_reg, arg0, 0, 0); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, 0xffffL); - tcg_out_insn(s, RRE, NGR, data_reg, 13); + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, 0xffffL); + tcg_out_insn(s, RRE, NGR, data_reg, TCG_TMP0); #endif break; case LD_INT16: @@ -802,16 +806,16 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, (tcg_target_long)s->code_ptr) >> 1; if (off == (int32_t)off) { /* load address relative to PC */ - tcg_out_insn(s, RIL, LARL, TCG_REG_R13, off); + tcg_out_insn(s, RIL, LARL, TCG_TMP0, off); } else { /* too far for larl */ - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, + tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (tcg_target_long)(s->tb_next + args[0])); } /* load address stored at s->tb_next + args[0] */ - tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R13, TCG_REG_R13, 0); + tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_TMP0, 0); /* and go there */ - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R13); + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_TMP0); } s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf; break; @@ -934,9 +938,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_neg_i64: /* FIXME: optimize args[0] != args[1] case */ - tcg_out_mov(s, TCG_REG_R13, args[1]); + tcg_out_mov(s, TCG_TMP0, args[1]); tcg_out_movi(s, TCG_TYPE_I64, args[0], 0); - tcg_out_insn(s, RRE, SGR, args[0], TCG_REG_R13); + tcg_out_insn(s, RRE, SGR, args[0], TCG_TMP0); break; case INDEX_op_mul_i32: @@ -1192,7 +1196,7 @@ void tcg_target_init(TCGContext *s) tcg_regset_clear(s->reserved_regs); /* frequently used as a temporary */ - tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); + tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* another temporary */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R12); /* XXX many insns can't be used with R0, so we better avoid it for now */