Patchwork [05/35] tcg-s390: Icache flush is a no-op.

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Submitter Richard Henderson
Date June 4, 2010, 7:14 p.m.
Message ID <1275678883-7082-6-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/54672/
State New
Headers show

Comments

Richard Henderson - June 4, 2010, 7:14 p.m.
Before gcc 4.2, __builtin___clear_cache doesn't exist, and
afterward the gcc s390 backend implements it as nothing.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/s390/tcg-target.h |    5 -----
 1 files changed, 0 insertions(+), 5 deletions(-)
Aurelien Jarno - June 9, 2010, 10:55 p.m.
On Fri, Jun 04, 2010 at 12:14:13PM -0700, Richard Henderson wrote:
> Before gcc 4.2, __builtin___clear_cache doesn't exist, and
> afterward the gcc s390 backend implements it as nothing.

Does it means that instruction and data caches are coherent on s390?

> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/s390/tcg-target.h |    5 -----
>  1 files changed, 0 insertions(+), 5 deletions(-)
> 
> diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
> index d8a2955..d7fe0c7 100644
> --- a/tcg/s390/tcg-target.h
> +++ b/tcg/s390/tcg-target.h
> @@ -94,9 +94,4 @@ enum {
>  
>  static inline void flush_icache_range(unsigned long start, unsigned long stop)
>  {
> -#if QEMU_GNUC_PREREQ(4, 1)
> -    __builtin___clear_cache((char *) start, (char *) stop);
> -#else
> -#error not implemented
> -#endif
>  }
> -- 
> 1.7.0.1
> 
> 
>
Richard Henderson - June 10, 2010, 10:04 p.m.
On 06/09/2010 03:55 PM, Aurelien Jarno wrote:
> On Fri, Jun 04, 2010 at 12:14:13PM -0700, Richard Henderson wrote:
>> Before gcc 4.2, __builtin___clear_cache doesn't exist, and
>> afterward the gcc s390 backend implements it as nothing.
> 
> Does it means that instruction and data caches are coherent on s390?

Yes.

Principles of Operation, 2.1 Main storage:
# Main storage may include a faster-access buffer storage, sometimes called a cache.
# Each CPU may have an associated cache. The effects, except on  performance, of
# the physical construction and the use of distinct storage media are not observable
# by the program.

This architecture pre-dates caches, I think.  ;-)


r~
Aurelien Jarno - June 11, 2010, 6:46 a.m.
On Thu, Jun 10, 2010 at 03:04:04PM -0700, Richard Henderson wrote:
> On 06/09/2010 03:55 PM, Aurelien Jarno wrote:
> > On Fri, Jun 04, 2010 at 12:14:13PM -0700, Richard Henderson wrote:
> >> Before gcc 4.2, __builtin___clear_cache doesn't exist, and
> >> afterward the gcc s390 backend implements it as nothing.
> > 
> > Does it means that instruction and data caches are coherent on s390?
> 
> Yes.
> 
> Principles of Operation, 2.1 Main storage:
> # Main storage may include a faster-access buffer storage, sometimes called a cache.
> # Each CPU may have an associated cache. The effects, except on  performance, of
> # the physical construction and the use of distinct storage media are not observable
> # by the program.
> 
> This architecture pre-dates caches, I think.  ;-)

Ok, I have applied the patch

Patch

diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index d8a2955..d7fe0c7 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -94,9 +94,4 @@  enum {
 
 static inline void flush_icache_range(unsigned long start, unsigned long stop)
 {
-#if QEMU_GNUC_PREREQ(4, 1)
-    __builtin___clear_cache((char *) start, (char *) stop);
-#else
-#error not implemented
-#endif
 }