| Message ID | 1447958344-836-2-git-send-email-geert+renesas@glider.be |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
Hi Geert, Thank you for the patch. On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote: > Amend the DT bindings to include the optional external clock on > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input, > depending on board wiring. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Cc: devicetree@vger.kernel.org > --- > Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index > 2c9e6b8477e92792..8efc9b6f35637fbb 100644 > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > @@ -43,6 +43,9 @@ Required properties: > - clocks: Must contain a phandle and clock-specifier pair for each entry > in clock-names. > - clock-names: Must contain "fck" for the SCIx UART functional clock. > + On (H)SCI(F) and some SCIFA, an additional clock may be specified: Could you list the SCIFA variants that support external clocks ? > + - "hsck" for the optional external clock input (on HSCIF), > + - "sck" for the optional external clock input (on other variants). > > Note: Each enabled SCIx UART should have an alias correctly numbered in the > "aliases" node.
Hi Geert, On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote: > On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote: > > Amend the DT bindings to include the optional external clock on > > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input, > > depending on board wiring. > > > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > > Cc: devicetree@vger.kernel.org > > --- > > > > Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 3 +++ > > 1 file changed, 3 insertions(+) > > > > diff --git > > a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > > b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index > > 2c9e6b8477e92792..8efc9b6f35637fbb 100644 > > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > > > > @@ -43,6 +43,9 @@ Required properties: > > - clocks: Must contain a phandle and clock-specifier pair for each > > entry > > > > in clock-names. > > > > - clock-names: Must contain "fck" for the SCIx UART functional clock. > > > > + On (H)SCI(F) and some SCIFA, an additional clock may be specified: > Could you list the SCIFA variants that support external clocks ? > > > + - "hsck" for the optional external clock input (on HSCIF), > > + - "sck" for the optional external clock input (on other variants). Additionally, those clocks are used as inputs to the baud rate generator for external clocks, as the ones listed in patch 02/25 in this series. I'd merge the two patches and clarify the wording. > > Note: Each enabled SCIx UART should have an alias correctly numbered in > > the "aliases" node.
Hi Laurent, On Thu, Nov 19, 2015 at 9:19 PM, Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote: >> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index >> 2c9e6b8477e92792..8efc9b6f35637fbb 100644 >> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> @@ -43,6 +43,9 @@ Required properties: >> - clocks: Must contain a phandle and clock-specifier pair for each entry >> in clock-names. >> - clock-names: Must contain "fck" for the SCIx UART functional clock. >> + On (H)SCI(F) and some SCIFA, an additional clock may be specified: > > Could you list the SCIFA variants that support external clocks ? The list is in the commit description of "[PATCH 19/25] serial: sh-sci: Add support for optional external (H)SCK input": sh7723, sh7724, and r8a7740. Note that the list is probably incomplete, so I don't know if it's that useful to have it in the binding docs. Especially as I haven't verified yet that it actually works ;-) Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Nov 19, 2015 at 9:27 PM, Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote: >> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote: >> > Amend the DT bindings to include the optional external clock on >> > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input, >> > depending on board wiring. >> > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> > >> > @@ -43,6 +43,9 @@ Required properties: >> > - clocks: Must contain a phandle and clock-specifier pair for each >> > entry >> > >> > in clock-names. >> > >> > - clock-names: Must contain "fck" for the SCIx UART functional clock. >> > >> > + On (H)SCI(F) and some SCIFA, an additional clock may be specified: >> Could you list the SCIFA variants that support external clocks ? >> >> > + - "hsck" for the optional external clock input (on HSCIF), >> > + - "sck" for the optional external clock input (on other variants). > > Additionally, those clocks are used as inputs to the baud rate generator for > external clocks, as the ones listed in patch 02/25 in this series. I'd merge > the two patches and clarify the wording. "SCK" predates the BRG, it even exists on SCI in H8/300. That SCK is used as input to the BRG is just an artefact of how the BRG was added to the SCIF. The BRG is just muxed with the existing SCK to form a clock input, which is muxed with the BRR clock through the SCSCR.CKEx bits. And the BRG itself can choose between SCIF_CLK and INT_CLK. Hence that's why I split it in two parts. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Geert, On Thursday 19 November 2015 21:39:50 Geert Uytterhoeven wrote: > On Thu, Nov 19, 2015 at 9:27 PM, Laurent Pinchart wrote: > > On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote: > >> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote: > >> > Amend the DT bindings to include the optional external clock on > >> > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input, > >> > depending on board wiring. > >> > > >> > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > >> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt > >> > > >> > @@ -43,6 +43,9 @@ Required properties: > >> > - clocks: Must contain a phandle and clock-specifier pair for each > >> > entry in clock-names. > >> > - clock-names: Must contain "fck" for the SCIx UART functional > >> > clock. > >> > + On (H)SCI(F) and some SCIFA, an additional clock may be specified: > >> > >> Could you list the SCIFA variants that support external clocks ? > >> > >> > + - "hsck" for the optional external clock input (on HSCIF), > >> > + - "sck" for the optional external clock input (on other > >> > variants). > > > > Additionally, those clocks are used as inputs to the baud rate generator > > for external clocks, as the ones listed in patch 02/25 in this series. > > I'd merge the two patches and clarify the wording. > > "SCK" predates the BRG, it even exists on SCI in H8/300. > > That SCK is used as input to the BRG is just an artefact of how the BRG was > added to the SCIF. The BRG is just muxed with the existing SCK to form a > clock input, which is muxed with the BRR clock through the SCSCR.CKEx bits. > And the BRG itself can choose between SCIF_CLK and INT_CLK. > > Hence that's why I split it in two parts. It makes sense with the explanation. I think some of the patches should be clarified to mention BRG-EC (or whatever you want to call it) instead of just BRG, as otherwise it's very easy to confuse the two BRGs. The (H)SCK clock is an input to the internal BRG, while the SCIF_CLK and INT_CLK are inputs to the BRG-EC. Without clarification the DT bindings and the code can be hard to understand.
Hi Laurent, On Thu, Nov 19, 2015 at 10:17 PM, Laurent Pinchart <laurent.pinchart@ideasonboard.com> wrote: > On Thursday 19 November 2015 21:39:50 Geert Uytterhoeven wrote: >> On Thu, Nov 19, 2015 at 9:27 PM, Laurent Pinchart wrote: >> > On Thursday 19 November 2015 22:19:14 Laurent Pinchart wrote: >> >> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote: >> >> > Amend the DT bindings to include the optional external clock on >> >> > (H)SCI(F) and some SCIFA, where this pin can serve as a clock input, >> >> > depending on board wiring. >> >> > >> >> > --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> >> > +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >> >> > >> >> > @@ -43,6 +43,9 @@ Required properties: >> >> > - clocks: Must contain a phandle and clock-specifier pair for each >> >> > entry in clock-names. >> >> > - clock-names: Must contain "fck" for the SCIx UART functional >> >> > clock. >> >> > + On (H)SCI(F) and some SCIFA, an additional clock may be specified: >> >> >> >> Could you list the SCIFA variants that support external clocks ? >> >> >> >> > + - "hsck" for the optional external clock input (on HSCIF), >> >> > + - "sck" for the optional external clock input (on other >> >> > variants). >> > >> > Additionally, those clocks are used as inputs to the baud rate generator >> > for external clocks, as the ones listed in patch 02/25 in this series. >> > I'd merge the two patches and clarify the wording. >> >> "SCK" predates the BRG, it even exists on SCI in H8/300. >> >> That SCK is used as input to the BRG is just an artefact of how the BRG was >> added to the SCIF. The BRG is just muxed with the existing SCK to form a >> clock input, which is muxed with the BRR clock through the SCSCR.CKEx bits. >> And the BRG itself can choose between SCIF_CLK and INT_CLK. >> >> Hence that's why I split it in two parts. > > It makes sense with the explanation. > > I think some of the patches should be clarified to mention BRG-EC (or whatever > you want to call it) instead of just BRG, as otherwise it's very easy to > confuse the two BRGs. The (H)SCK clock is an input to the internal BRG, while > the SCIF_CLK and INT_CLK are inputs to the BRG-EC. Without clarification the > DT bindings and the code can be hard to understand. The (H)SCK clock is not an input to the internal BRG: it's used directly as the sampling clock. I'll add more clarification... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Thu, Nov 19, 2015 at 9:33 PM, Geert Uytterhoeven <geert@linux-m68k.org> wrote: > On Thu, Nov 19, 2015 at 9:19 PM, Laurent Pinchart > <laurent.pinchart@ideasonboard.com> wrote: >> On Thursday 19 November 2015 19:38:40 Geert Uytterhoeven wrote: >>> diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >>> b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index >>> 2c9e6b8477e92792..8efc9b6f35637fbb 100644 >>> --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >>> +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt >>> @@ -43,6 +43,9 @@ Required properties: >>> - clocks: Must contain a phandle and clock-specifier pair for each entry >>> in clock-names. >>> - clock-names: Must contain "fck" for the SCIx UART functional clock. >>> + On (H)SCI(F) and some SCIFA, an additional clock may be specified: >> >> Could you list the SCIFA variants that support external clocks ? > > The list is in the commit description of "[PATCH 19/25] serial: sh-sci: Add > support for optional external (H)SCK input": sh7723, sh7724, and r8a7740. > > Note that the list is probably incomplete, so I don't know if it's that useful > to have it in the binding docs. Especially as I haven't verified yet that it > actually works ;-) For the record: on r8a7740, this feature is not available on SCIFA instances 2-7. The sole pins providing access to SCIFA_SCK[01] are muxed for Ethernet use on r8a7740/armadillo. So it's unlikely I'll be able to support and test this. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt index 2c9e6b8477e92792..8efc9b6f35637fbb 100644 --- a/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt +++ b/Documentation/devicetree/bindings/serial/renesas,sci-serial.txt @@ -43,6 +43,9 @@ Required properties: - clocks: Must contain a phandle and clock-specifier pair for each entry in clock-names. - clock-names: Must contain "fck" for the SCIx UART functional clock. + On (H)SCI(F) and some SCIFA, an additional clock may be specified: + - "hsck" for the optional external clock input (on HSCIF), + - "sck" for the optional external clock input (on other variants). Note: Each enabled SCIx UART should have an alias correctly numbered in the "aliases" node.
Amend the DT bindings to include the optional external clock on (H)SCI(F) and some SCIFA, where this pin can serve as a clock input, depending on board wiring. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Cc: devicetree@vger.kernel.org --- Documentation/devicetree/bindings/serial/renesas,sci-serial.txt | 3 +++ 1 file changed, 3 insertions(+)