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[U-Boot] Revert "net: phy: delay only if reset handler is registered"

Message ID CAOMZO5BMP67EUxDuC50UFwf3RW=re07smf7Q4Kg+2jeKLXvHQw@mail.gmail.com
State Changes Requested
Delegated to: Stefano Babic
Headers show

Commit Message

Fabio Estevam Nov. 18, 2015, 11:30 a.m. UTC 
Hi Stefan,

On Wed, Nov 18, 2015 at 3:54 AM, Stefan Roese <stefan.roese@gmail.com> wrote:

> I'm not sure if this revert is the right way to solve this problem.
> Please take a look at my answer a few weeks ago:
>
> https://www.mail-archive.com/u-boot@lists.denx.de/msg191206.html
>
> As mentioned in my mail above, the delay should be added after
> the deassertion of the PHY reset signal. And not here in
> phy_find_by_mask() for all boards.
>
> I just checked the code in mx6sxsabresd.c. Here also the delay is
> missing:
>
>         /* Reset AR8031 PHY */
>         gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
>         udelay(500);
>         gpio_set_value(IMX_GPIO_NR(2, 7), 1);
>
> Could you please test with this change:
>
>         /* Reset AR8031 PHY */
>         gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
>         udelay(500);
>         gpio_set_value(IMX_GPIO_NR(2, 7), 1);
> +       udelay(1500);
>
> Or even better, check how long the reset needs to be inactive
> before the PHY starts to work.

Sure, I have even tried:


and it does not work here:

U-Boot 2016.01-rc1-00022-gfe52456-dirty (Nov 18 2015 - 09:28:02 -0200)

CPU:   Freescale i.MX6SX rev1.0 996 MHz (running at 792 MHz)
CPU:   Extended Commercial temperature grade (-20C to 105C) at 44C
Reset cause: POR
Board: MX6SX SABRE SDB
I2C:   ready
DRAM:  1 GiB
PMIC:  PFUZE100 ID=0x10
MMC:   FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
PCI:   pcie phy link never came up
In:    serial
Out:   serial
Err:   serial
Net:   Board Net Initialization Failed
No ethernet found.
Hit any key to stop autoboot:  0
Booting from net ...
No ethernet found.
No ethernet found.
Bad Linux ARM zImage magic!

Regards,

Fabio Estevam
diff mbox

Patch

--- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c
+++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c
@@ -163,8 +163,9 @@  static int setup_fec(void)

        /* Reset AR8031 PHY */
        gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
-       udelay(500);
+       udelay(50000);
        gpio_set_value(IMX_GPIO_NR(2, 7), 1);
+       udelay(50000);

        reg = readl(&anatop->pll_enet);
        reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;