From patchwork Fri Jun 4 08:39:53 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chen huacai X-Patchwork-Id: 54547 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3D2ABB7D30 for ; Fri, 4 Jun 2010 18:40:17 +1000 (EST) Received: from localhost ([127.0.0.1]:33185 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKSRp-0003BL-L6 for incoming@patchwork.ozlabs.org; Fri, 04 Jun 2010 04:40:13 -0400 Received: from [140.186.70.92] (port=59547 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKSQF-00039l-21 for qemu-devel@nongnu.org; Fri, 04 Jun 2010 04:38:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OKSQ3-0005yS-Qs for qemu-devel@nongnu.org; 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Fri, 04 Jun 2010 01:38:22 -0700 (PDT) Received: from localhost.localdomain ([211.69.198.200]) by mx.google.com with ESMTPS id 23sm667625pzk.2.2010.06.04.01.38.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 04 Jun 2010 01:38:21 -0700 (PDT) From: Huacai Chen To: aurelien@aurel32.net Date: Fri, 4 Jun 2010 16:39:53 +0800 Message-Id: <1275640793-15385-1-git-send-email-zltjiangshi@gmail.com> X-Mailer: git-send-email 1.7.0.4 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: blauwirbel@gmail.com, qemu-devel@nongnu.org, Huacai Chen Subject: [Qemu-devel] [PATCH v3 5/7] MIPS: Initial support of fulong mini pc (CPU definition) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Huacai Chen --- target-mips/mips-defs.h | 4 ++++ target-mips/translate_init.c | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+), 0 deletions(-) diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h index c57de02..38594da 100644 --- a/target-mips/mips-defs.h +++ b/target-mips/mips-defs.h @@ -40,6 +40,8 @@ #define ASE_SMARTMIPS 0x00040000 /* Chip specific instructions. */ +#define INSN_LOONGSON2E 0x20000000 +#define INSN_LOONGSON2F 0x40000000 #define INSN_VR54XX 0x80000000 /* MIPS CPU defines. */ @@ -48,6 +50,8 @@ #define CPU_MIPS3 (CPU_MIPS2 | ISA_MIPS3) #define CPU_MIPS4 (CPU_MIPS3 | ISA_MIPS4) #define CPU_VR54XX (CPU_MIPS4 | INSN_VR54XX) +#define CPU_LOONGSON2E (CPU_MIPS3 | INSN_LOONGSON2E) +#define CPU_LOONGSON2F (CPU_MIPS3 | INSN_LOONGSON2F) #define CPU_MIPS5 (CPU_MIPS4 | ISA_MIPS5) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index b79ed56..0d9899e 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -454,6 +454,41 @@ static const mips_def_t mips_defs[] = .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, .mmu_type = MMU_TYPE_R4000, }, + { + .name = "Loongson-2E", + .CP0_PRid = 0x6302, + /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ + .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | + (0x1<<4) | (0x1<<1), + /* Note: Config1 is only used internally, Loongson-2E has only Config0. */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x35D0FFFF, + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), + .SEGBITS = 40, + .PABITS = 40, + .insn_flags = CPU_LOONGSON2E, + .mmu_type = MMU_TYPE_R4000, + }, + { + .name = "Loongson-2F", + .CP0_PRid = 0x6303, + /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/ + .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) | + (0x1<<4) | (0x1<<1), + /* Note: Config1 is only used internally, Loongson-2F has only Config0. */ + .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), + .SYNCI_Step = 16, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writeable*/ + .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), + .SEGBITS = 40, + .PABITS = 40, + .insn_flags = CPU_LOONGSON2F, + .mmu_type = MMU_TYPE_R4000, + }, + #endif };