Message ID | 1447702479-6997-2-git-send-email-serge.fdrv@gmail.com |
---|---|
State | New |
Headers | show |
On 16.11.2015 22:34, Sergey Fedorov wrote: > Coprocessor access instructions are allowed inside IT block. > gen_helper_access_check_cp_reg() can raise an exceptions thus condexec > bits should be updated before. > > Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> > --- > target-arm/translate.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 4351854..f1f8129 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) > break; > } > > + gen_set_condexec(dc); Ah, there must be gen_set_condexec(s). > gen_set_pc_im(s, s->pc - 4); > tmpptr = tcg_const_ptr(ri); > tcg_syn = tcg_const_i32(syndrome);
On 17 November 2015 at 10:59, Sergey Fedorov <serge.fdrv@gmail.com> wrote: > On 16.11.2015 22:34, Sergey Fedorov wrote: >> Coprocessor access instructions are allowed inside IT block. >> gen_helper_access_check_cp_reg() can raise an exceptions thus condexec >> bits should be updated before. >> >> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> >> --- >> target-arm/translate.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/target-arm/translate.c b/target-arm/translate.c >> index 4351854..f1f8129 100644 >> --- a/target-arm/translate.c >> +++ b/target-arm/translate.c >> @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) >> break; >> } >> >> + gen_set_condexec(dc); > > Ah, there must be gen_set_condexec(s). Yep. Are you going to resend? thanks -- PMM
On 17.11.2015 16:31, Peter Maydell wrote: > On 17 November 2015 at 10:59, Sergey Fedorov <serge.fdrv@gmail.com> wrote: >> On 16.11.2015 22:34, Sergey Fedorov wrote: >>> Coprocessor access instructions are allowed inside IT block. >>> gen_helper_access_check_cp_reg() can raise an exceptions thus condexec >>> bits should be updated before. >>> >>> Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> >>> --- >>> target-arm/translate.c | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/target-arm/translate.c b/target-arm/translate.c >>> index 4351854..f1f8129 100644 >>> --- a/target-arm/translate.c >>> +++ b/target-arm/translate.c >>> @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) >>> break; >>> } >>> >>> + gen_set_condexec(dc); >> Ah, there must be gen_set_condexec(s). > Yep. Are you going to resend? I got sort of ahead of myself with the patch. Yes, I will resend it now. Best, Sergey
diff --git a/target-arm/translate.c b/target-arm/translate.c index 4351854..f1f8129 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7210,6 +7210,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) break; } + gen_set_condexec(dc); gen_set_pc_im(s, s->pc - 4); tmpptr = tcg_const_ptr(ri); tcg_syn = tcg_const_i32(syndrome);
Coprocessor access instructions are allowed inside IT block. gen_helper_access_check_cp_reg() can raise an exceptions thus condexec bits should be updated before. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> --- target-arm/translate.c | 1 + 1 file changed, 1 insertion(+)