===================================================================
@@ -571,6 +571,7 @@ extern int rs6000_vector_align[];
#define TARGET_FCTIWUZ TARGET_POPCNTD
#define TARGET_CTZ TARGET_MODULO
#define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64)
+#define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64)
#define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
#define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR)
===================================================================
@@ -2837,6 +2837,14 @@ (define_expand "<u>mul<mode><dmode>3"
DONE;
})
+(define_insn "*maddld4"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+ (plus:DI (mult:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+ (match_operand:DI 2 "gpc_reg_operand" "r"))
+ (match_operand:DI 3 "gpc_reg_operand" "r")))]
+ "TARGET_MADDLD"
+ "maddld %0,%1,%2,%3"
+ [(set_attr "type" "mul")])
(define_insn "udiv<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
===================================================================
@@ -0,0 +1,20 @@
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-require-effective-target powerpc_p9modulo_ok } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+
+long
+s_madd (long a, long b, long c)
+{
+ return (a * b) + c;
+}
+
+unsigned long
+u_madd (unsigned long a, unsigned long b, unsigned long c)
+{
+ return (a * b) + c;
+}
+
+/* { dg-final { scan-assembler-times "maddld " 2 } } */
+/* { dg-final { scan-assembler-not "mulld " } } */
+/* { dg-final { scan-assembler-not "add " } } */