commit c5a3ade022a18dad02d3391aab7af9ddf7e26340
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date: Fri Aug 14 13:42:51 2015 +0100
[ARM][3/3] Implement negsicc, notsicc optabs
@@ -10079,19 +10079,43 @@ (define_insn "*ifcompare_neg_move"
(set_attr "type" "multiple")]
)
-(define_insn_and_split "*if_neg_move"
+;; The negsicc and notsicc optabs.
+(define_expand "<NOT_NEG_op>sicc"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+ (if_then_else:SI (match_operand 1 "arm_comparison_operator" "")
+ (NOT_NEG:SI (match_operand:SI 2 "s_register_operand" ""))
+ (match_operand:SI 3 "s_register_operand" "")))]
+ "TARGET_32BIT"
+ {
+ rtx ccreg;
+ enum rtx_code code = GET_CODE (operands[1]);
+
+ if (code == UNEQ || code == LTGT)
+ FAIL;
+
+ ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0),
+ XEXP (operands[1], 1), NULL);
+ operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx);
+ }
+)
+
+
+(define_insn_and_split "*if_<NOT_NEG_op>_move"
[(set (match_operand:SI 0 "s_register_operand" "=l,r")
(if_then_else:SI
(match_operator 4 "arm_comparison_operator"
[(match_operand 3 "cc_register" "") (const_int 0)])
- (neg:SI (match_operand:SI 2 "s_register_operand" "l,r"))
+ (NOT_NEG:SI (match_operand:SI 2 "s_register_operand" "l,r"))
(match_operand:SI 1 "s_register_operand" "0,0")))]
"TARGET_32BIT"
"#"
"&& reload_completed"
[(cond_exec (match_op_dup 4 [(match_dup 3) (const_int 0)])
- (set (match_dup 0) (neg:SI (match_dup 2))))]
- ""
+ (set (match_dup 0) (NOT_NEG:SI (match_dup 2))))]
+ {
+ if (!rtx_equal_p (operands[0], operands[1]))
+ emit_move_insn (operands[0], operands[1]);
+ }
[(set_attr "conds" "use")
(set_attr "length" "4")
(set_attr "arch" "t2,32")
@@ -209,6 +209,9 @@ (define_code_iterator COMPARISONS [eq gt ge le lt])
;; A list of ...
(define_code_iterator IOR_XOR [ior xor])
+;; Bitwise complement and negation
+(define_code_iterator NOT_NEG [not neg])
+
;; Operations on two halves of a quadword vector.
(define_code_iterator VQH_OPS [plus smin smax umin umax])
@@ -656,6 +659,8 @@ (define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax")
(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u")
(umax "u")])
+(define_code_attr NOT_NEG_op [(not "not") (neg "neg")])
+
(define_code_attr cnb [(ltu "CC_C") (geu "CC")])
(define_code_attr optab [(ltu "ltu") (geu "geu")])
new file mode 100644
@@ -0,0 +1,42 @@
+/* { dg-do run } */
+/* { dg-options "-save-temps -O2 -fno-inline" } */
+/* { dg-require-effective-target arm_cond_exec } */
+
+extern void abort (void);
+
+#define N 25089992
+
+int
+foonegsi (int a)
+{
+ return a ? N : -N;
+}
+
+int
+fooinvsi (int a)
+{
+ return a ? N : ~N;
+}
+
+
+
+int
+main (void)
+{
+ if (foonegsi (1) != N)
+ abort ();
+
+ if (foonegsi (0) != -N)
+ abort ();
+
+ if (fooinvsi (1) != N)
+ abort ();
+
+ if (fooinvsi (0) != ~N)
+ abort ();
+
+ return 0;
+}
+
+/* { dg-final { scan-assembler "rsbne" } } */
+/* { dg-final { scan-assembler "mvnne" } } */
Hi all, This is a slight respin of https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00075.html. This had been ok'd but I've encountered a bug with the *if_<NOT_NEG_op>_move pattern For some reason, after reload operands[1] doesn't end up living in the same register as operands[0] even though it has the constraint '0'. Maybe I misunderstood the semantics of the '0' constraints. In any case, telling the splitter to explicitly emit the move before the cond_exec if the registers don't match fixes this. Bootstrapped and tested on arm. Ok to commit this updated version instead? Thanks, Kyrill 2015-11-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * config/arm/arm.md (<NOT_NEG_op>sicc): New define_expand. (*if_neg_move): Rename to... (*if_<NOT_NEG_op>_move): ... This. Use NOT_NEG code iterator. Move operands[1] into operands[0] if they don't match up. * config/arm/iterators.md (NOT_NEG): New code iterator. (NOT_NEG_op): New code attribute. 2015-11-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com> * gcc.target/arm/cond_op_imm_1.c: New test.