From patchwork Mon May 31 15:54:21 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: cmchao X-Patchwork-Id: 54115 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 8F9D8B7D6F for ; Tue, 1 Jun 2010 02:37:28 +1000 (EST) Received: from localhost ([127.0.0.1]:40097 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OJ7yy-0006Ck-O7 for incoming@patchwork.ozlabs.org; Mon, 31 May 2010 12:36:56 -0400 Received: from [140.186.70.92] (port=52940 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OJ7fk-00073z-4N for qemu-devel@nongnu.org; Mon, 31 May 2010 12:17:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OJ7Kk-0001mn-RN for qemu-devel@nongnu.org; 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Mon, 31 May 2010 08:55:21 -0700 (PDT) Received: from localhost.localdomain (114-44-102-240.dynamic.hinet.net [114.44.102.240]) by mx.google.com with ESMTPS id f11sm50661974wai.23.2010.05.31.08.55.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 31 May 2010 08:55:21 -0700 (PDT) From: cmchao To: qemu-devel@nongnu.org Date: Mon, 31 May 2010 23:54:21 +0800 Message-Id: <1275321264-1131-10-git-send-email-cmchao@gmail.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1275321264-1131-1-git-send-email-cmchao@gmail.com> References: <1275321264-1131-1-git-send-email-cmchao@gmail.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Subject: [Qemu-devel] [PATCH v2 09/12] hw/omap2.c : separate tap module(Test-Chip-level) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: cmchao --- Makefile.target | 2 +- hw/omap2.c | 90 -------------------------------------------- hw/omap_tap.c | 112 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 113 insertions(+), 91 deletions(-) create mode 100644 hw/omap_tap.c diff --git a/Makefile.target b/Makefile.target index d532dc8..b80d5e0 100644 --- a/Makefile.target +++ b/Makefile.target @@ -265,7 +265,7 @@ obj-arm-y += pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o pxa2xx_keypad.o obj-arm-y += gumstix.o obj-arm-y += zaurus.o ide/microdrive.o spitz.o tosa.o tc6393xb.o obj-arm-y += omap1.o omap_lcdc.o omap_dma.o omap_clk.o omap_mmc.o omap_i2c.o omap_gpio.o omap_intc.o -obj-arm-y += omap2.o omap_dss.o soc_dma.o omap_gptimer.o omap_synctimer.o omap_gpmc.o omap_sdrc.o omap_spi.o +obj-arm-y += omap2.o omap_dss.o soc_dma.o omap_gptimer.o omap_synctimer.o omap_gpmc.o omap_sdrc.o omap_spi.o omap_tap.o obj-arm-y += omap_sx1.o palm.o tsc210x.o obj-arm-y += nseries.o blizzard.o onenand.o vga.o cbus.o tusb6010.o usb-musb.o obj-arm-y += mst_fpga.o mainstone.o diff --git a/hw/omap2.c b/hw/omap2.c index ae6394e..7403077 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -1245,96 +1245,6 @@ target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region, return base; } -/* TEST-Chip-level TAP */ -static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr) -{ - struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; - - switch (addr) { - case 0x204: /* IDCODE_reg */ - switch (s->mpu_model) { - case omap2420: - case omap2422: - case omap2423: - return 0x5b5d902f; /* ES 2.2 */ - case omap2430: - return 0x5b68a02f; /* ES 2.2 */ - case omap3430: - return 0x1b7ae02f; /* ES 2 */ - default: - hw_error("%s: Bad mpu model\n", __FUNCTION__); - } - - case 0x208: /* PRODUCTION_ID_reg for OMAP2 */ - case 0x210: /* PRODUCTION_ID_reg for OMAP3 */ - switch (s->mpu_model) { - case omap2420: - return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ - case omap2422: - return 0x000400f0; - case omap2423: - return 0x000800f0; - case omap2430: - return 0x000000f0; - case omap3430: - return 0x000000f0; - default: - hw_error("%s: Bad mpu model\n", __FUNCTION__); - } - - case 0x20c: - switch (s->mpu_model) { - case omap2420: - case omap2422: - case omap2423: - return 0xcafeb5d9; /* ES 2.2 */ - case omap2430: - return 0xcafeb68a; /* ES 2.2 */ - case omap3430: - return 0xcafeb7ae; /* ES 2 */ - default: - hw_error("%s: Bad mpu model\n", __FUNCTION__); - } - - case 0x218: /* DIE_ID_reg */ - return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); - case 0x21c: /* DIE_ID_reg */ - return 0x54 << 24; - case 0x220: /* DIE_ID_reg */ - return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); - case 0x224: /* DIE_ID_reg */ - return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); - } - - OMAP_BAD_REG(addr); - return 0; -} - -static void omap_tap_write(void *opaque, target_phys_addr_t addr, - uint32_t value) -{ - OMAP_BAD_REG(addr); -} - -static CPUReadMemoryFunc * const omap_tap_readfn[] = { - omap_badwidth_read32, - omap_badwidth_read32, - omap_tap_read, -}; - -static CPUWriteMemoryFunc * const omap_tap_writefn[] = { - omap_badwidth_write32, - omap_badwidth_write32, - omap_tap_write, -}; - -void omap_tap_init(struct omap_target_agent_s *ta, - struct omap_mpu_state_s *mpu) -{ - omap_l4_attach(ta, 0, l4_register_io_memory( - omap_tap_readfn, omap_tap_writefn, mpu)); -} - /* Power, Reset, and Clock Management */ struct omap_prcm_s { qemu_irq irq[3]; diff --git a/hw/omap_tap.c b/hw/omap_tap.c new file mode 100644 index 0000000..1f18ddd --- /dev/null +++ b/hw/omap_tap.c @@ -0,0 +1,112 @@ +/* + * TI OMAP TEST-Chip-level TAP emulation. + * + * Copyright (C) 2007-2008 Nokia Corporation + * Written by Andrzej Zaborowski + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) any later version of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "hw.h" +#include "omap.h" + +/* TEST-Chip-level TAP */ +static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr) +{ + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque; + + switch (addr) { + case 0x204: /* IDCODE_reg */ + switch (s->mpu_model) { + case omap2420: + case omap2422: + case omap2423: + return 0x5b5d902f; /* ES 2.2 */ + case omap2430: + return 0x5b68a02f; /* ES 2.2 */ + case omap3430: + return 0x1b7ae02f; /* ES 2 */ + default: + hw_error("%s: Bad mpu model\n", __FUNCTION__); + } + + case 0x208: /* PRODUCTION_ID_reg for OMAP2 */ + case 0x210: /* PRODUCTION_ID_reg for OMAP3 */ + switch (s->mpu_model) { + case omap2420: + return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */ + case omap2422: + return 0x000400f0; + case omap2423: + return 0x000800f0; + case omap2430: + return 0x000000f0; + case omap3430: + return 0x000000f0; + default: + hw_error("%s: Bad mpu model\n", __FUNCTION__); + } + + case 0x20c: + switch (s->mpu_model) { + case omap2420: + case omap2422: + case omap2423: + return 0xcafeb5d9; /* ES 2.2 */ + case omap2430: + return 0xcafeb68a; /* ES 2.2 */ + case omap3430: + return 0xcafeb7ae; /* ES 2 */ + default: + hw_error("%s: Bad mpu model\n", __FUNCTION__); + } + + case 0x218: /* DIE_ID_reg */ + return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); + case 0x21c: /* DIE_ID_reg */ + return 0x54 << 24; + case 0x220: /* DIE_ID_reg */ + return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); + case 0x224: /* DIE_ID_reg */ + return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0); + } + + OMAP_BAD_REG(addr); + return 0; +} + +static void omap_tap_write(void *opaque, target_phys_addr_t addr, + uint32_t value) +{ + OMAP_BAD_REG(addr); +} + +static CPUReadMemoryFunc * const omap_tap_readfn[] = { + omap_badwidth_read32, + omap_badwidth_read32, + omap_tap_read, +}; + +static CPUWriteMemoryFunc * const omap_tap_writefn[] = { + omap_badwidth_write32, + omap_badwidth_write32, + omap_tap_write, +}; + +void omap_tap_init(struct omap_target_agent_s *ta, + struct omap_mpu_state_s *mpu) +{ + omap_l4_attach(ta, 0, l4_register_io_memory( + omap_tap_readfn, omap_tap_writefn, mpu)); +}