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[U-Boot,v1,2/7] driver/ddr/fsl: Update DDR4 MR6 for Vref range

Message ID 1446660203-18047-3-git-send-email-yorksun@freescale.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

York Sun Nov. 4, 2015, 6:03 p.m. UTC 
MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.

Signed-off-by: York Sun <yorksun@freescale.com>
---

 drivers/ddr/fsl/ctrl_regs.c |    3 +++
 1 file changed, 3 insertions(+)
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Patch

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 8543679..36bf647 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1186,6 +1186,9 @@  static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
 
 	esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
 
+	if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
+		esdmode6 |= 1 << 6;	/* Range 2 */
+
 	ddr->ddr_sdram_mode_10 = (0
 				 | ((esdmode6 & 0xffff) << 16)
 				 | ((esdmode7 & 0xffff) << 0)