From patchwork Sun May 30 22:35:46 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: sparc32 esp fix spurious interrupts in chip reset Date: Sun, 30 May 2010 12:35:46 -0000 From: Artyom Tarasenko X-Patchwork-Id: 54007 Message-Id: <1275258946-15739-1-git-send-email-atar4qemu@gmail.com> To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, Artyom Tarasenko lower interrupt during chip reset. Otherwise the ESP_RSTAT register may get out of sync with the IRQ line status. This effect became visible after commit 65899fe3 Signed-off-by: Artyom Tarasenko --- hw/esp.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/hw/esp.c b/hw/esp.c index 0a8cf6e..0532c67 100644 --- a/hw/esp.c +++ b/hw/esp.c @@ -423,6 +423,7 @@ static void esp_reset(DeviceState *d) { ESPState *s = container_of(d, ESPState, busdev.qdev); + esp_lower_irq(s); memset(s->rregs, 0, ESP_REGS); memset(s->wregs, 0, ESP_REGS); s->rregs[ESP_TCHI] = TCHI_FAS100A; // Indicate fas100a