Patchwork sparc32 SuperSPARC MMU Breakpoint Action register (SS-20 OBP fix)

login
register
mail settings
Submitter Artyom Tarasenko
Date May 29, 2010, 8:48 p.m.
Message ID <1275166105-4277-1-git-send-email-atar4qemu@gmail.com>
Download mbox | patch
Permalink /patch/53987/
State New
Headers show

Comments

Artyom Tarasenko - May 29, 2010, 8:48 p.m.
SuperSPARC MMU Breakpoint Action register is used by OBP at boot

The patch allows booting Solaris and some other OS with
SPARCStation-20 OBP.

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
---
 target-sparc/op_helper.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)
Blue Swirl - May 29, 2010, 9:27 p.m.
Thanks, applied.

On Sat, May 29, 2010 at 8:48 PM, Artyom Tarasenko
<atar4qemu@googlemail.com> wrote:
> SuperSPARC MMU Breakpoint Action register is used by OBP at boot
>
> The patch allows booting Solaris and some other OS with
> SPARCStation-20 OBP.
>
> Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
> ---
>  target-sparc/op_helper.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
> index aaacfc4..ef3504f 100644
> --- a/target-sparc/op_helper.c
> +++ b/target-sparc/op_helper.c
> @@ -1745,6 +1745,7 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
>     case 0x31: // Turbosparc RAM snoop
>     case 0x32: // Turbosparc page table descriptor diagnostic
>     case 0x39: /* data cache diagnostic register */
> +    case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
>         ret = 0;
>         break;
>     case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
> --
> 1.6.2.5
>
>

Patch

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index aaacfc4..ef3504f 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -1745,6 +1745,7 @@  uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
     case 0x31: // Turbosparc RAM snoop
     case 0x32: // Turbosparc page table descriptor diagnostic
     case 0x39: /* data cache diagnostic register */
+    case 0x4c: /* SuperSPARC MMU Breakpoint Action register */
         ret = 0;
         break;
     case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */