@@ -1592,6 +1592,26 @@ static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
address_space_init(&proxy->modern_as, &proxy->modern_cfg, "virtio-pci-cfg-as");
+ if (!(proxy->flags & VIRTIO_PCI_FLAG_DISABLE_PCIE)
+ && !(proxy->flags & VIRTIO_PCI_FLAG_DISABLE_MODERN)
+ && pci_bus_is_express(pci_dev->bus)
+ && !pci_bus_is_root(pci_dev->bus)) {
+ int pos;
+
+ pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
+ pos = pcie_endpoint_cap_init(pci_dev, 0);
+ assert(pos > 0);
+
+ pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF);
+ assert(pos > 0);
+
+ /*
+ * Indicates that this function complies with revision 1.2 of the
+ * PCI Power Management Interface Specification.
+ */
+ pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);
+ }
+
virtio_pci_bus_new(&proxy->bus, sizeof(proxy->bus), proxy);
if (k->realize) {
k->realize(proxy, errp);
@@ -1622,6 +1642,8 @@ static Property virtio_pci_properties[] = {
VIRTIO_PCI_FLAG_DISABLE_LEGACY_BIT, false),
DEFINE_PROP_BIT("disable-modern", VirtIOPCIProxy, flags,
VIRTIO_PCI_FLAG_DISABLE_MODERN_BIT, true),
+ DEFINE_PROP_BIT("disable-pcie", VirtIOPCIProxy, flags,
+ VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT, false),
DEFINE_PROP_END_OF_LIST(),
};
@@ -72,8 +72,10 @@ typedef struct VirtioBusClass VirtioPCIBusClass;
/* virtio version flags */
#define VIRTIO_PCI_FLAG_DISABLE_LEGACY_BIT 2
#define VIRTIO_PCI_FLAG_DISABLE_MODERN_BIT 3
+#define VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT 4
#define VIRTIO_PCI_FLAG_DISABLE_LEGACY (1 << VIRTIO_PCI_FLAG_DISABLE_LEGACY_BIT)
#define VIRTIO_PCI_FLAG_DISABLE_MODERN (1 << VIRTIO_PCI_FLAG_DISABLE_MODERN_BIT)
+#define VIRTIO_PCI_FLAG_DISABLE_PCIE (1 << VIRTIO_PCI_FLAG_DISABLE_PCIE_BIT)
typedef struct {
MSIMessage msg;
@@ -2,7 +2,11 @@
#define HW_COMPAT_H
#define HW_COMPAT_2_4 \
- /* empty */
+ {\
+ .driver = "virtio-pci",\
+ .property = "disable-pcie",\
+ .value = "on",\
+ },
#define HW_COMPAT_2_3 \
{\
The virtio devices are converted to PCI-Express if they are plugged into a PCI-Express bus and the 'modern' protocol is enabled. Devices plugged directly into the Root Complex as Integrated Endpoints remain PCI. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> --- v3 -> v4: - Addressed Eduardo Habkost's comments: - used a single virtio-pci.disable-pcie=on entry for HW_COMPAT, instead of one entry for each subclass v2 -> v3: - Addressed Michael S. Tsirkin's comments: - enable pcie only for 2.5+ machines. v1 -> v2: - Addressed Michael S. Tsirkin's comments: - Added the minimum required capabilities for PCIe devices - Integrated Endpoints remain PCI - Use pcie_endpoint_cap_init instead of manually creating the pcie capability. - Regarding Gerd Hoffman's comments: - Creating virtio-pcie devices: For the moment I prefer to not duplicate the virtio definitions, at least until we don't have a consensus (Personally I don't like it) - Removing the IO bar: This would be my next patch on the "virtio to express" series, I plan to remove it only for "modern" devices. Thanks, Marcel hw/virtio/virtio-pci.c | 22 ++++++++++++++++++++++ hw/virtio/virtio-pci.h | 2 ++ include/hw/compat.h | 6 +++++- 3 files changed, 29 insertions(+), 1 deletion(-)