From patchwork Thu May 27 20:46:25 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 53838 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7393DB7D1D for ; Fri, 28 May 2010 08:18:38 +1000 (EST) Received: from localhost ([127.0.0.1]:43146 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHlPO-000111-QT for incoming@patchwork.ozlabs.org; Thu, 27 May 2010 18:18:34 -0400 Received: from [140.186.70.92] (port=56295 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHjzX-0002I2-Fj for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OHjzW-0005RU-36 for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:47 -0400 Received: from are.twiddle.net ([75.149.56.221]:51253) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OHjzV-0005RP-Q9 for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:46 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id 2F1FA576; Thu, 27 May 2010 13:47:45 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o4RKlisd031018; Thu, 27 May 2010 13:47:44 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o4RKlhd2031017; Thu, 27 May 2010 13:47:43 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 May 2010 13:46:25 -0700 Message-Id: <1274993204-30766-44-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1274993204-30766-1-git-send-email-rth@twiddle.net> References: <1274993204-30766-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 43/62] tcg-s390: Tidy tcg_prepare_qemu_ldst. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Make use of the reg+reg+disp addressing mode to eliminate redundant additions. Make use of the load-and-operate insns. Avoid an extra register copy when using the 64-bit shift insns. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 56 ++++++++++++++++-------------------------------- 1 files changed, 19 insertions(+), 37 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 5d2efaa..000a646 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -135,6 +135,7 @@ typedef enum S390Opcode { RS_SRA = 0x8a, RS_SRL = 0x88, + RXY_AG = 0xe308, RXY_CG = 0xe320, RXY_LB = 0xe376, RXY_LG = 0xe304, @@ -962,24 +963,16 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg, { const TCGReg arg0 = TCG_REG_R2; const TCGReg arg1 = TCG_REG_R3; - const TCGReg arg2 = TCG_REG_R4; - int s_bits; + int s_bits = opc & 3; uint16_t *label1_ptr; + tcg_target_long ofs; - if (is_store) { - s_bits = opc; + if (TARGET_LONG_BITS == 32) { + tgen_ext32u(s, arg0, addr_reg); } else { - s_bits = opc & 3; + tcg_out_mov(s, arg0, addr_reg); } -#if TARGET_LONG_BITS == 32 - tgen_ext32u(s, arg1, addr_reg); - tgen_ext32u(s, arg0, addr_reg); -#else - tcg_out_mov(s, arg1, addr_reg); - tcg_out_mov(s, arg0, addr_reg); -#endif - tcg_out_sh64(s, RSY_SRLG, arg1, addr_reg, SH64_REG_NONE, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); @@ -987,17 +980,19 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg, tgen64_andi(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS); if (is_store) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, - offsetof(CPUState, tlb_table[mem_index][0].addr_write)); + ofs = offsetof(CPUState, tlb_table[mem_index][0].addr_write); } else { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, - offsetof(CPUState, tlb_table[mem_index][0].addr_read)); + ofs = offsetof(CPUState, tlb_table[mem_index][0].addr_read); } - tcg_out_insn(s, RRE, AGR, arg1, TCG_TMP0); + assert(ofs < 0x80000); - tcg_out_insn(s, RRE, AGR, arg1, TCG_AREG0); + tcg_out_insn(s, RXY, CG, arg0, arg1, TCG_AREG0, ofs); - tcg_out_insn(s, RXY, CG, arg0, arg1, 0, 0); + if (TARGET_LONG_BITS == 32) { + tgen_ext32u(s, arg0, addr_reg); + } else { + tcg_out_mov(s, arg0, addr_reg); + } label1_ptr = (uint16_t*)s->code_ptr; @@ -1005,15 +1000,9 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg, tcg_out_insn(s, RI, BRC, S390_CC_EQ, 0); /* call load/store helper */ -#if TARGET_LONG_BITS == 32 - tgen_ext32u(s, arg0, addr_reg); -#else - tcg_out_mov(s, arg0, addr_reg); -#endif - if (is_store) { tcg_out_mov(s, arg1, data_reg); - tcg_out_movi(s, TCG_TYPE_I32, arg2, mem_index); + tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R4, mem_index); tgen_calli(s, (tcg_target_ulong)qemu_st_helpers[s_bits]); } else { tcg_out_movi(s, TCG_TYPE_I32, arg1, mem_index); @@ -1046,17 +1035,10 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, TCGReg data_reg, *(label1_ptr + 1) = ((unsigned long)s->code_ptr - (unsigned long)label1_ptr) >> 1; - if (is_store) { - tcg_out_insn(s, RXY, LG, arg1, arg1, 0, - offsetof(CPUTLBEntry, addend) - - offsetof(CPUTLBEntry, addr_write)); - } else { - tcg_out_insn(s, RXY, LG, arg1, arg1, 0, - offsetof(CPUTLBEntry, addend) - - offsetof(CPUTLBEntry, addr_read)); - } + ofs = offsetof(CPUState, tlb_table[mem_index][0].addend); + assert(ofs < 0x80000); - tcg_out_insn(s, RRE, AGR, arg0, arg1); + tcg_out_insn(s, RXY, AG, arg0, arg1, TCG_AREG0, ofs); } static void tcg_finish_qemu_ldst(TCGContext* s, uint16_t *label2_ptr)