Patchwork [45/62] tcg-s390: Implement GUEST_BASE.

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Submitter Richard Henderson
Date May 27, 2010, 8:46 p.m.
Message ID <1274993204-30766-46-git-send-email-rth@twiddle.net>
Download mbox | patch
Permalink /patch/53833/
State New
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Richard Henderson - May 27, 2010, 8:46 p.m.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 configure             |    2 ++
 tcg/s390/tcg-target.c |   30 +++++++++++++++++++++++++-----
 tcg/s390/tcg-target.h |    2 ++
 3 files changed, 29 insertions(+), 5 deletions(-)

Patch

diff --git a/configure b/configure
index 72d3df8..56dee88 100755
--- a/configure
+++ b/configure
@@ -698,10 +698,12 @@  case "$cpu" in
            ;;
     s390)
            QEMU_CFLAGS="-march=z990 $QEMU_CFLAGS"
+           host_guest_base="yes"
            ;;
     s390x)
            QEMU_CFLAGS="-m64 -march=z9-109 $QEMU_CFLAGS"
            LDFLAGS="-m64 $LDFLAGS"
+           host_guest_base="yes"
            ;;
     i386)
            QEMU_CFLAGS="-m32 $QEMU_CFLAGS"
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index fa089ab..4a3235c 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -33,10 +33,20 @@ 
     do { } while (0)
 #endif
 
-#define TCG_CT_CONST_S32                0x100
-#define TCG_CT_CONST_N32                0x200
+#define TCG_CT_CONST_S32   0x100
+#define TCG_CT_CONST_N32   0x200
 
-#define TCG_TMP0                        TCG_REG_R14
+#define TCG_TMP0           TCG_REG_R14
+
+#ifdef CONFIG_USE_GUEST_BASE
+#define TCG_GUEST_BASE_REG TCG_REG_R13
+#else
+#define TCG_GUEST_BASE_REG TCG_REG_R0
+#endif
+
+#ifndef GUEST_BASE
+#define GUEST_BASE 0
+#endif
 
 
 /* All of the following instructions are prefixed with their instruction
@@ -1051,12 +1061,17 @@  static void tcg_finish_qemu_ldst(TCGContext* s, uint16_t *label2_ptr)
 static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
                                   TCGReg *index_reg, tcg_target_long *disp)
 {
-    *index_reg = 0;
-    *disp = 0;
     if (TARGET_LONG_BITS == 32) {
         tgen_ext32u(s, TCG_TMP0, *addr_reg);
         *addr_reg = TCG_TMP0;
     }
+    if (GUEST_BASE < 0x80000) {
+        *index_reg = 0;
+        *disp = GUEST_BASE;
+    } else {
+        *index_reg = TCG_GUEST_BASE_REG;
+        *disp = 0;
+    }
 }
 #endif /* CONFIG_SOFTMMU */
 
@@ -1682,6 +1697,11 @@  void tcg_target_qemu_prologue(TCGContext *s)
     /* aghi %r15,-160 (stack frame) */
     tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -160);
 
+    if (GUEST_BASE >= 0x80000) {
+        tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
+        tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
+    }
+
     /* br %r2 (go to TB) */
     tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R2);
 
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index fae8ed7..940f530 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -83,6 +83,8 @@  typedef enum TCGReg {
 // #define TCG_TARGET_HAS_nand_i64
 // #define TCG_TARGET_HAS_nor_i64
 
+#define TCG_TARGET_HAS_GUEST_BASE
+
 /* used for function call generation */
 #define TCG_REG_CALL_STACK		TCG_REG_R15
 #define TCG_TARGET_STACK_ALIGN		8