From patchwork Thu May 27 20:46:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 53811 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9EB25B7D2D for ; Fri, 28 May 2010 07:28:17 +1000 (EST) Received: from localhost ([127.0.0.1]:51168 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHkcZ-00032U-1F for incoming@patchwork.ozlabs.org; Thu, 27 May 2010 17:28:07 -0400 Received: from [140.186.70.92] (port=55953 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHjz5-00020v-Oo for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OHjz4-0005JH-60 for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:19 -0400 Received: from are.twiddle.net ([75.149.56.221]:51209) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OHjz3-0005J6-T8 for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:18 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id 506B2F1D; Thu, 27 May 2010 13:47:17 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o4RKlGjD030925; Thu, 27 May 2010 13:47:16 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o4RKlFHL030924; Thu, 27 May 2010 13:47:15 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 May 2010 13:46:04 -0700 Message-Id: <1274993204-30766-23-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1274993204-30766-1-git-send-email-rth@twiddle.net> References: <1274993204-30766-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 22/62] tcg-s390: Tidy branches. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add tgen_gotoi to implement conditional and unconditional direct branches. Add tgen_branch to implement branches to labels. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 96 ++++++++++++++++++++++++++++--------------------- 1 files changed, 55 insertions(+), 41 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 21ad1a3..f4dab1a 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -41,8 +41,9 @@ halves of the 16-bit quantity may appear 32 bits apart in the insn. This makes it easy to copy the values from the tables in Appendix B. */ typedef enum S390Opcode { - RIL_LARL = 0xc000, RIL_BRASL = 0xc005, + RIL_BRCL = 0xc004, + RIL_LARL = 0xc000, RI_AGHI = 0xa70b, RI_AHI = 0xa70a, @@ -175,17 +176,27 @@ static const int tcg_target_call_oarg_regs[] = { /* signed/unsigned is handled by using COMPARE and COMPARE LOGICAL, respectively */ + +#define S390_CC_EQ 8 +#define S390_CC_LT 4 +#define S390_CC_GT 2 +#define S390_CC_OV 1 +#define S390_CC_NE (S390_CC_LT | S390_CC_GT) +#define S390_CC_LE (S390_CC_LT | S390_CC_EQ) +#define S390_CC_GE (S390_CC_GT | S390_CC_EQ) +#define S390_CC_ALWAYS 15 + static const uint8_t tcg_cond_to_s390_cond[10] = { - [TCG_COND_EQ] = 8, - [TCG_COND_LT] = 4, - [TCG_COND_LTU] = 4, - [TCG_COND_LE] = 8 | 4, - [TCG_COND_LEU] = 8 | 4, - [TCG_COND_GT] = 2, - [TCG_COND_GTU] = 2, - [TCG_COND_GE] = 8 | 2, - [TCG_COND_GEU] = 8 | 2, - [TCG_COND_NE] = 4 | 2 | 1, + [TCG_COND_EQ] = S390_CC_EQ, + [TCG_COND_LT] = S390_CC_LT, + [TCG_COND_LTU] = S390_CC_LT, + [TCG_COND_LE] = S390_CC_LE, + [TCG_COND_LEU] = S390_CC_LE, + [TCG_COND_GT] = S390_CC_GT, + [TCG_COND_GTU] = S390_CC_GT, + [TCG_COND_GE] = S390_CC_GE, + [TCG_COND_GEU] = S390_CC_GE, + [TCG_COND_NE] = S390_CC_NE, }; #ifdef CONFIG_SOFTMMU @@ -455,6 +466,31 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond c, tcg_out_movi(s, type, dest, 0); } +static void tgen_gotoi(TCGContext *s, int cc, tcg_target_long dest) +{ + tcg_target_long off = (dest - (tcg_target_long)s->code_ptr) >> 1; + if (off > -0x8000 && off < 0x7fff) { + tcg_out_insn(s, RI, BRC, cc, off); + } else if (off == (int32_t)off) { + tcg_out_insn(s, RIL, BRCL, cc, off); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, dest); + tcg_out_insn(s, RR, BCR, cc, TCG_REG_R13); + } +} + +static void tgen_branch(TCGContext *s, int cc, int labelno) +{ + TCGLabel* l = &s->labels[labelno]; + if (l->has_value) { + tgen_gotoi(s, cc, l->u.value); + } else { + tcg_out16(s, RIL_BRCL | (cc << 4)); + tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, labelno, -2); + s->code_ptr += 4; + } +} + #if defined(CONFIG_SOFTMMU) static void tcg_prepare_qemu_ldst(TCGContext* s, int data_reg, int addr_reg, int mem_index, int opc, @@ -507,7 +543,7 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, int data_reg, int addr_reg, label1_ptr = (uint16_t*)s->code_ptr; /* je label1 (offset will be patched in later) */ - tcg_out_insn(s, RI, BRC, 8, 0); + tcg_out_insn(s, RI, BRC, S390_CC_EQ, 0); /* call load/store helper */ #if TARGET_LONG_BITS == 32 @@ -551,7 +587,7 @@ static void tcg_prepare_qemu_ldst(TCGContext* s, int data_reg, int addr_reg, /* jump to label2 (end) */ *label2_ptr_p = (uint16_t*)s->code_ptr; - tcg_out_insn(s, RI, BRC, 15, 0); + tcg_out_insn(s, RI, BRC, S390_CC_ALWAYS, 0); /* this is label1, patch branch */ *(label1_ptr + 1) = ((unsigned long)s->code_ptr - @@ -734,16 +770,13 @@ static void tcg_out_qemu_st(TCGContext* s, const TCGArg* args, int opc) static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { - TCGLabel* l; S390Opcode op; switch (opc) { case INDEX_op_exit_tb: /* return value */ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, args[0]); - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, (unsigned long)tb_ret_addr); - /* br %r13 */ - tcg_out_insn(s, RR, BCR, 15, TCG_REG_R13); + tgen_gotoi(s, S390_CC_ALWAYS, (unsigned long)tb_ret_addr); break; case INDEX_op_goto_tb: @@ -763,7 +796,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, /* load address stored at s->tb_next + args[0] */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R13, TCG_REG_R13, 0); /* and go there */ - tcg_out_insn(s, RR, BASR, TCG_REG_R13, TCG_REG_R13); + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R13); } s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf; break; @@ -971,16 +1004,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, goto do_shift64; case INDEX_op_br: - l = &s->labels[args[0]]; - if (l->has_value) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, l->u.value); - } else { - /* larl %r13, ... */ - tcg_out16(s, RIL_LARL | (TCG_REG_R13 << 4)); - tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, args[0], -2); - s->code_ptr += 4; - } - tcg_out_insn(s, RR, BASR, TCG_REG_R13, TCG_REG_R13); + tgen_branch(s, S390_CC_ALWAYS, args[0]); break; case INDEX_op_brcond_i64: @@ -989,17 +1013,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_brcond_i32: tgen32_cmp(s, args[2], args[0], args[1]); do_brcond: - l = &s->labels[args[3]]; - if (l->has_value) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R13, l->u.value); - } else { - /* larl %r13, ... */ - tcg_out16(s, RIL_LARL | (TCG_REG_R13 << 4)); - tcg_out_reloc(s, s->code_ptr, R_390_PC32DBL, args[3], -2); - s->code_ptr += 4; - } - /* bcr cond, %r13 */ - tcg_out_insn(s, RR, BCR, tcg_cond_to_s390_cond[args[2]], TCG_REG_R13); + tgen_branch(s, tcg_cond_to_s390_cond[args[2]], args[3]); break; case INDEX_op_setcond_i32: @@ -1194,7 +1208,7 @@ void tcg_target_qemu_prologue(TCGContext *s) tcg_out_insn(s, RI, AGHI, TCG_REG_R15, -160); /* br %r2 (go to TB) */ - tcg_out_insn(s, RR, BCR, 15, TCG_REG_R2); + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R2); tb_ret_addr = s->code_ptr; @@ -1202,7 +1216,7 @@ void tcg_target_qemu_prologue(TCGContext *s) tcg_out_insn(s, RXY, LMG, TCG_REG_R6, TCG_REG_R15, TCG_REG_R15, 208); /* br %r14 (return) */ - tcg_out_insn(s, RR, BCR, 15, TCG_REG_R14); + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_R14); } static inline void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)