From patchwork Thu May 27 20:46:06 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 53806 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A7107B7D1C for ; Fri, 28 May 2010 07:22:55 +1000 (EST) Received: from localhost ([127.0.0.1]:56955 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHkXT-0000Fh-73 for incoming@patchwork.ozlabs.org; Thu, 27 May 2010 17:22:51 -0400 Received: from [140.186.70.92] (port=56003 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHjz8-00022b-GR for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OHjz6-0005KH-Uz for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:22 -0400 Received: from are.twiddle.net ([75.149.56.221]:51216) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OHjz6-0005Jx-K9 for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:20 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id 07D25A32; Thu, 27 May 2010 13:47:20 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o4RKlJfi030933; Thu, 27 May 2010 13:47:19 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o4RKlIXX030932; Thu, 27 May 2010 13:47:18 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 May 2010 13:46:06 -0700 Message-Id: <1274993204-30766-25-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1274993204-30766-1-git-send-email-rth@twiddle.net> References: <1274993204-30766-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 24/62] tcg-s390: Implement div2. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The s390 divide instructions always produce both remainder and quotient. Since TCG has no mechanism for allocating even+odd register pairs, force the use of the R2/R3 register pair. Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 44 ++++++++++++++++++++++++++++++-------------- tcg/s390/tcg-target.h | 4 ++-- 2 files changed, 32 insertions(+), 16 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 0bd4276..4c2acca 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -75,6 +75,7 @@ typedef enum S390Opcode { RR_BCR = 0x07, RR_CLR = 0x15, RR_CR = 0x19, + RR_DR = 0x1d, RR_LCR = 0x13, RR_LR = 0x18, RR_NR = 0x14, @@ -258,6 +259,14 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) case 'R': /* not R0 */ tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); break; + case 'a': /* force R2 for division */ + tcg_regset_clear(ct->u.regs); + tcg_regset_set_reg(ct->u.regs, TCG_REG_R2); + break; + case 'b': /* force R3 for division */ + tcg_regset_clear(ct->u.regs); + tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); + break; case 'I': ct->ct &= ~TCG_CT_REG; ct->ct |= TCG_CT_CONST_S16; @@ -946,16 +955,22 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, RRE, MSGR, args[0], args[2]); break; - case INDEX_op_divu_i32: - case INDEX_op_remu_i32: - tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R12, 0); - tcg_out_insn(s, RR, LR, TCG_REG_R13, args[1]); - tcg_out_insn(s, RRE, DLR, TCG_REG_R12, args[2]); - if (opc == INDEX_op_divu_i32) { - tcg_out_insn(s, RR, LR, args[0], TCG_REG_R13); /* quotient */ - } else { - tcg_out_insn(s, RR, LR, args[0], TCG_REG_R12); /* remainder */ - } + case INDEX_op_div2_i32: + tcg_out_insn(s, RR, DR, TCG_REG_R2, args[4]); + break; + case INDEX_op_divu2_i32: + tcg_out_insn(s, RRE, DLR, TCG_REG_R2, args[4]); + break; + + case INDEX_op_div2_i64: + /* ??? We get an unnecessary sign-extension of the dividend + into R3 with this definition, but as we do in fact always + produce both quotient and remainder using INDEX_op_div_i64 + instead requires jumping through even more hoops. */ + tcg_out_insn(s, RRE, DSGR, TCG_REG_R2, args[4]); + break; + case INDEX_op_divu2_i64: + tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]); break; case INDEX_op_shl_i32: @@ -1085,10 +1100,8 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_sub_i32, { "r", "0", "r" } }, { INDEX_op_mul_i32, { "r", "0", "r" } }, - { INDEX_op_div_i32, { "r", "r", "r" } }, - { INDEX_op_divu_i32, { "r", "r", "r" } }, - { INDEX_op_rem_i32, { "r", "r", "r" } }, - { INDEX_op_remu_i32, { "r", "r", "r" } }, + { INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } }, + { INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } }, { INDEX_op_and_i32, { "r", "0", "r" } }, { INDEX_op_or_i32, { "r", "0", "r" } }, @@ -1137,6 +1150,9 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_sub_i64, { "r", "0", "r" } }, { INDEX_op_mul_i64, { "r", "0", "r" } }, + { INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } }, + { INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } }, + { INDEX_op_and_i64, { "r", "0", "r" } }, { INDEX_op_or_i64, { "r", "0", "r" } }, { INDEX_op_xor_i64, { "r", "0", "r" } }, diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index c81f886..b987a7e 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -48,7 +48,7 @@ typedef enum TCGReg { #define TCG_TARGET_NB_REGS 16 /* optional instructions */ -#define TCG_TARGET_HAS_div_i32 +#define TCG_TARGET_HAS_div2_i32 // #define TCG_TARGET_HAS_rot_i32 // #define TCG_TARGET_HAS_ext8s_i32 // #define TCG_TARGET_HAS_ext16s_i32 @@ -64,7 +64,7 @@ typedef enum TCGReg { // #define TCG_TARGET_HAS_nand_i32 // #define TCG_TARGET_HAS_nor_i32 -// #define TCG_TARGET_HAS_div_i64 +#define TCG_TARGET_HAS_div2_i64 // #define TCG_TARGET_HAS_rot_i64 // #define TCG_TARGET_HAS_ext8s_i64 // #define TCG_TARGET_HAS_ext16s_i64