From patchwork Thu May 27 20:46:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 53794 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 2AB72B7D1C for ; Fri, 28 May 2010 07:06:05 +1000 (EST) Received: from localhost ([127.0.0.1]:60680 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHkHC-0000Gr-6a for incoming@patchwork.ozlabs.org; Thu, 27 May 2010 17:06:02 -0400 Received: from [140.186.70.92] (port=56063 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OHjzC-00025C-Dc for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OHjzA-0005Lk-Vb for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:26 -0400 Received: from are.twiddle.net ([75.149.56.221]:51221) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OHjzA-0005LO-Ml for qemu-devel@nongnu.org; Thu, 27 May 2010 16:47:24 -0400 Received: from anchor.twiddle.home (anchor.twiddle.home [172.31.0.4]) by are.twiddle.net (Postfix) with ESMTPS id 0C30CA32; Thu, 27 May 2010 13:47:24 -0700 (PDT) Received: from anchor.twiddle.home (anchor.twiddle.home [127.0.0.1]) by anchor.twiddle.home (8.14.4/8.14.4) with ESMTP id o4RKlNpH030945; Thu, 27 May 2010 13:47:23 -0700 Received: (from rth@localhost) by anchor.twiddle.home (8.14.4/8.14.4/Submit) id o4RKlMka030944; Thu, 27 May 2010 13:47:22 -0700 From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 27 May 2010 13:46:09 -0700 Message-Id: <1274993204-30766-28-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.0.1 In-Reply-To: <1274993204-30766-1-git-send-email-rth@twiddle.net> References: <1274993204-30766-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: agraf@suse.de, aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 27/62] tcg-s390: Implement bswap operations. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.c | 24 ++++++++++++++++++++++++ tcg/s390/tcg-target.h | 10 +++++----- 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c index 3f7d08d..7c7adb3 100644 --- a/tcg/s390/tcg-target.c +++ b/tcg/s390/tcg-target.c @@ -78,6 +78,8 @@ typedef enum S390Opcode { RRE_LLGCR = 0xb984, RRE_LLGFR = 0xb916, RRE_LLGHR = 0xb985, + RRE_LRVR = 0xb91f, + RRE_LRVGR = 0xb90f, RRE_MSGR = 0xb90c, RRE_MSR = 0xb252, RRE_NGR = 0xb980, @@ -1117,6 +1119,21 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tgen_ext32u(s, args[0], args[1]); break; + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + /* The TCG bswap definition requires bits 0-47 already be zero. + Thus we don't need the G-type insns to implement bswap16_i64. */ + tcg_out_insn(s, RRE, LRVR, args[0], args[1]); + tcg_out_insn(s, RS, SRL, args[0], 0, SH32_REG_NONE, 16); + break; + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + tcg_out_insn(s, RRE, LRVR, args[0], args[1]); + break; + case INDEX_op_bswap64_i64: + tcg_out_insn(s, RRE, LRVGR, args[0], args[1]); + break; + case INDEX_op_br: tgen_branch(s, S390_CC_ALWAYS, args[0]); break; @@ -1229,6 +1246,9 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_ext16s_i32, { "r", "r" } }, { INDEX_op_ext16u_i32, { "r", "r" } }, + { INDEX_op_bswap16_i32, { "r", "r" } }, + { INDEX_op_bswap32_i32, { "r", "r" } }, + { INDEX_op_brcond_i32, { "r", "r" } }, { INDEX_op_setcond_i32, { "r", "r", "r" } }, @@ -1286,6 +1306,10 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_ext32s_i64, { "r", "r" } }, { INDEX_op_ext32u_i64, { "r", "r" } }, + { INDEX_op_bswap16_i64, { "r", "r" } }, + { INDEX_op_bswap32_i64, { "r", "r" } }, + { INDEX_op_bswap64_i64, { "r", "r" } }, + { INDEX_op_brcond_i64, { "r", "r" } }, { INDEX_op_setcond_i64, { "r", "r", "r" } }, #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 76a13fc..76f1d03 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -54,8 +54,8 @@ typedef enum TCGReg { #define TCG_TARGET_HAS_ext16s_i32 #define TCG_TARGET_HAS_ext8u_i32 #define TCG_TARGET_HAS_ext16u_i32 -// #define TCG_TARGET_HAS_bswap16_i32 -// #define TCG_TARGET_HAS_bswap32_i32 +#define TCG_TARGET_HAS_bswap16_i32 +#define TCG_TARGET_HAS_bswap32_i32 // #define TCG_TARGET_HAS_not_i32 #define TCG_TARGET_HAS_neg_i32 // #define TCG_TARGET_HAS_andc_i32 @@ -72,9 +72,9 @@ typedef enum TCGReg { #define TCG_TARGET_HAS_ext8u_i64 #define TCG_TARGET_HAS_ext16u_i64 #define TCG_TARGET_HAS_ext32u_i64 -// #define TCG_TARGET_HAS_bswap16_i64 -// #define TCG_TARGET_HAS_bswap32_i64 -// #define TCG_TARGET_HAS_bswap64_i64 +#define TCG_TARGET_HAS_bswap16_i64 +#define TCG_TARGET_HAS_bswap32_i64 +#define TCG_TARGET_HAS_bswap64_i64 // #define TCG_TARGET_HAS_not_i64 #define TCG_TARGET_HAS_neg_i64 // #define TCG_TARGET_HAS_andc_i64