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[PULL,v2,00/27] target-arm queue

Message ID 1445962043-2175-1-git-send-email-peter.maydell@linaro.org
State New
Headers show

Pull-request

git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151027-1

Message

Peter Maydell Oct. 27, 2015, 4:07 p.m. UTC
Version 2, with a fix for a 32-bit build failure squashed in.

thanks
-- PMM



The following changes since commit 7e038b94e74e1c2d1b3598e2e4b0b5c8b79a7278:

  Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2015-10-27 10:10:46 +0000)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151027-1

for you to fetch changes up to 9b539263faa5c1b7fce2551092b5c7b6eea92081:

  target-arm: Add support for S1 + S2 MMU translations (2015-10-27 15:59:47 +0000)

----------------------------------------------------------------
target-arm queue:
 * more EL2 preparation: handling for stage 2 translations
 * standardize debug macros in i.MX devices
 * improve error message in a corner case for virt board
 * disable live migration of KVM GIC if the kernel can't handle it
 * add SPSR_(ABT|UND|IRQ|FIQ) registers
 * handle non-executable page-straddling Thumb instructions
 * fix a "no 64-bit EL2" assumption in arm_excp_unmasked()

----------------------------------------------------------------
Andrew Jones (1):
      hw/arm/virt: don't use a15memmap directly

Edgar E. Iglesias (14):
      target-arm: Add HPFAR_EL2
      target-arm: lpae: Make t0sz and t1sz signed integers
      target-arm: lpae: Move declaration of t0sz and t1sz
      target-arm: Add support for AArch32 S2 negative t0sz
      target-arm: lpae: Replace tsz with computed inputsize
      target-arm: lpae: Rename granule_sz to stride
      target-arm: Add computation of starting level for S2 PTW
      target-arm: Add support for S2 page-table protection bits
      target-arm: Avoid inline for get_phys_addr
      target-arm: Add ARMMMUFaultInfo
      target-arm: Add S2 translation to 64bit S1 PTWs
      target-arm: Add S2 translation to 32bit S1 PTWs
      target-arm: Route S2 MMU faults to EL2
      target-arm: Add support for S1 + S2 MMU translations

Jean-Christophe Dubois (8):
      i.MX: Standardize i.MX serial debug.
      i.MX: Standardize i.MX GPIO debug
      i.MX: Standardize i.MX I2C debug
      i.MX: Standardize i.MX AVIC debug
      i.MX: Standardize i.MX CCM debug
      i.MX: Standardize i.MX FEC debug
      i.MX: Standardize i.MX EPIT debug
      i.MX: Standardize i.MX GPT debug

Pavel Fedin (1):
      arm_gic_kvm: Disable live migration if not supported

Peter Maydell (2):
      target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked()
      target-arm/translate.c: Handle non-executable page-straddling Thumb insns

Soren Brinkmann (1):
      target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ)

 hw/arm/virt.c                    |  25 ++-
 hw/char/imx_serial.c             |  50 +++--
 hw/gpio/imx_gpio.c               |  27 +--
 hw/i2c/imx_i2c.c                 |  43 ++---
 hw/intc/arm_gic_kvm.c            |  22 +--
 hw/intc/imx_avic.c               |  44 ++---
 hw/misc/imx_ccm.c                |  34 ++--
 hw/net/imx_fec.c                 |  64 +++----
 hw/timer/imx_epit.c              |  48 ++---
 hw/timer/imx_gpt.c               |  56 +++---
 include/hw/intc/arm_gic_common.h |   1 +
 target-arm/cpu.h                 |  83 ++++++---
 target-arm/helper.c              | 388 ++++++++++++++++++++++++++++++++-------
 target-arm/internals.h           |  40 +++-
 target-arm/op_helper.c           |  18 +-
 target-arm/translate.c           |  45 ++++-
 16 files changed, 679 insertions(+), 309 deletions(-)

Comments

Peter Maydell Oct. 28, 2015, 2:01 p.m. UTC | #1
On 27 October 2015 at 16:07, Peter Maydell <peter.maydell@linaro.org> wrote:
> Version 2, with a fix for a 32-bit build failure squashed in.
>
> thanks
> -- PMM
>
>
>
> The following changes since commit 7e038b94e74e1c2d1b3598e2e4b0b5c8b79a7278:
>
>   Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2015-10-27 10:10:46 +0000)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20151027-1
>
> for you to fetch changes up to 9b539263faa5c1b7fce2551092b5c7b6eea92081:
>
>   target-arm: Add support for S1 + S2 MMU translations (2015-10-27 15:59:47 +0000)
>
> ----------------------------------------------------------------
> target-arm queue:
>  * more EL2 preparation: handling for stage 2 translations
>  * standardize debug macros in i.MX devices
>  * improve error message in a corner case for virt board
>  * disable live migration of KVM GIC if the kernel can't handle it
>  * add SPSR_(ABT|UND|IRQ|FIQ) registers
>  * handle non-executable page-straddling Thumb instructions
>  * fix a "no 64-bit EL2" assumption in arm_excp_unmasked()
>
> ----------------------------------------------------------------

Applied, thanks.

-- PMM