| Message ID | 7bda33ef4f5f0b9945d051b816746e6ca80da092.1445958286.git.michal.simek@xilinx.com |
|---|---|
| State | Superseded |
| Delegated to: | Joe Hershberger |
| Headers | show |
Hi Michal, On Tue, Oct 27, 2015 at 10:04 AM, Michal Simek <michal.simek@xilinx.com> wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Code is taken from Linux kernel driver. > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > drivers/net/phy/Makefile | 1 + > drivers/net/phy/phy.c | 3 + > drivers/net/phy/ti.c | 205 +++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 209 insertions(+) > create mode 100644 drivers/net/phy/ti.c > > diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile > index d096db87a276..9e4d4927e676 100644 > --- a/drivers/net/phy/Makefile > +++ b/drivers/net/phy/Makefile > @@ -24,4 +24,5 @@ obj-$(CONFIG_PHY_NATSEMI) += natsemi.o > obj-$(CONFIG_PHY_REALTEK) += realtek.o > obj-$(CONFIG_PHY_SMSC) += smsc.o > obj-$(CONFIG_PHY_TERANETICS) += teranetics.o > +obj-$(CONFIG_PHY_TI) += ti.o > obj-$(CONFIG_PHY_VITESSE) += vitesse.o > diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c > index a6023f1033ec..c6046e4abc4e 100644 > --- a/drivers/net/phy/phy.c > +++ b/drivers/net/phy/phy.c > @@ -484,6 +484,9 @@ int phy_init(void) > #ifdef CONFIG_PHY_TERANETICS > phy_teranetics_init(); > #endif > +#ifdef CONFIG_PHY_TI > + phy_ti_init(); > +#endif > #ifdef CONFIG_PHY_VITESSE > phy_vitesse_init(); > #endif > diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c > new file mode 100644 > index 000000000000..bb30450d7531 > --- /dev/null > +++ b/drivers/net/phy/ti.c > @@ -0,0 +1,205 @@ > +/* > + * TI PHY drivers > + * > + * SPDX-License-Identifier: GPL-2.0 > + * > + */ > +#include <common.h> > +#include <phy.h> > + > +/* TI DP83867 */ > +#define DP83867_DEVADDR 0x1f > + > +#define MII_DP83867_PHYCTRL 0x10 > +#define MII_DP83867_MICR 0x12 > +#define DP83867_CTRL 0x1f > + > +/* Extended Registers */ > +#define DP83867_RGMIICTL 0x0032 > +#define DP83867_RGMIIDCTL 0x0086 > + > +/* FIXME this is consolidated in the latest U-Boot version */ > +#define BIT(x) (1UL << (x)) Indeed. > +#define DP83867_SW_RESET (1 << 15) > +#define DP83867_SW_RESTART (1 << 14) > + > +/* MICR Interrupt bits */ > +#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) > +#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) > +#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) > +#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) > +#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) > +#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) > +#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) > +#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) > +#define MII_DP83867_MICR_WOL_INT_EN BIT(3) > +#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) > +#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) > +#define MII_DP83867_MICR_JABBER_INT_EN BIT(0) > + > +/* RGMIICTL bits */ > +#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) > +#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) > + > +/* PHY CTRL bits */ > +#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 > + > +/* RGMIIDCTL bits */ > +#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 > + > +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ > +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ > + > +/* MMD Access Control register fields */ > +#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ > +#define MII_MMD_CTRL_ADDR 0x0000 /* Address */ > +#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ > +#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ > +#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ > + > +/* FIXME: These indirect PHY writes should go into common code. */ By this comment, you mean common to this phy and other phys? Either fix or remove the comment. > +/** > + * phy_read_mmd_indirect - reads data from the MMD registers > + * @phydev: The PHY device bus > + * @prtad: MMD Address > + * @devad: MMD DEVAD > + * @addr: PHY address on the MII bus > + * > + * Description: it reads data from the MMD registers (clause 22 to access to > + * clause 45) of the specified phy address. > + * To read these register we have: register -> registers > + * 1) Write reg 13 // DEVAD > + * 2) Write reg 14 // MMD Address > + * 3) Write reg 13 // MMD Data Command for MMD DEVAD > + * 3) Read reg 14 // Read MMD data > + */ > +int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, > + int devad, int addr) > +{ > + int value = -1; > + > + /* Write the desired MMD Devad */ > + phy_write(phydev, addr, MII_MMD_CTRL, devad); > + > + /* Write the desired MMD register address */ > + phy_write(phydev, addr, MII_MMD_DATA, prtad); > + > + /* Select the Function : DATA with no post increment */ > + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); > + > + /* Read the content of the MMD's selected register */ > + value = phy_read(phydev, addr, MII_MMD_DATA); > + return value; > +} > + > +/** > + * phy_write_mmd_indirect - writes data to the MMD registers > + * @phydev: The PHY device > + * @prtad: MMD Address > + * @devad: MMD DEVAD > + * @addr: PHY address on the MII bus > + * @data: data to write in the MMD register > + * > + * Description: Write data from the MMD registers of the specified > + * phy address. > + * To write these register we have: > + * 1) Write reg 13 // DEVAD > + * 2) Write reg 14 // MMD Address > + * 3) Write reg 13 // MMD Data Command for MMD DEVAD > + * 3) Write reg 14 // Write MMD data > + */ > +void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, > + int devad, int addr, u32 data) > +{ > + /* Write the desired MMD Devad */ > + phy_write(phydev, addr, MII_MMD_CTRL, devad); > + > + /* Write the desired MMD register address */ > + phy_write(phydev, addr, MII_MMD_DATA, prtad); > + > + /* Select the Function : DATA with no post increment */ > + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); > + > + /* Write the data into MMD's selected register */ > + phy_write(phydev, addr, MII_MMD_DATA, data); > +} > + > +/** > + * phy_interface_is_rgmii - Convenience function for testing if a PHY interface > + * is RGMII (all variants) > + * @phydev: the phy_device struct > + */ > +static inline bool phy_interface_is_rgmii(struct phy_device *phydev) > +{ > + return phydev->interface >= PHY_INTERFACE_MODE_RGMII && > + phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; > +} > + > +/* User setting - can be taken from DTS */ > +#define RX_ID_DELAY 8 > +#define TX_ID_DELAY 0xa > +#define FIFO_DEPTH 1 > + > +static int dp83867_config(struct phy_device *phydev) > +{ > + unsigned int val, delay; > + int ret; > + > + /* Restart the PHY. */ > + val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); > + phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, > + val | DP83867_SW_RESTART); > + > + if (phy_interface_is_rgmii(phydev)) { > + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, > + (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); > + if (ret) > + return ret; > + } > + > + if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && > + (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { > + val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, > + DP83867_DEVADDR, phydev->addr); > + > + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) > + val |= (DP83867_RGMII_TX_CLK_DELAY_EN | > + DP83867_RGMII_RX_CLK_DELAY_EN); > + > + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) > + val |= DP83867_RGMII_TX_CLK_DELAY_EN; > + > + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) > + val |= DP83867_RGMII_RX_CLK_DELAY_EN; > + > + phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, > + DP83867_DEVADDR, phydev->addr, val); > + > + delay = (RX_ID_DELAY | > + (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); > + > + phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, > + DP83867_DEVADDR, phydev->addr, delay); > + } > + > + genphy_config_aneg(phydev); > + return 0; > +} > + > +static struct phy_driver DP83867_driver = { > + .name = "TI DP83867", > + .uid = 0x2000a231, > + .mask = 0xfffffff0, > + .features = PHY_GBIT_FEATURES, > + .config = &dp83867_config, > + .startup = &genphy_startup, > + .shutdown = &genphy_shutdown, > +}; > + > +int phy_ti_init(void) > +{ > + phy_register(&DP83867_driver); > + return 0; > +} > -- > 2.5.0 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot
On 11/02/2015 10:15 PM, Joe Hershberger wrote: > Hi Michal, > > On Tue, Oct 27, 2015 at 10:04 AM, Michal Simek <michal.simek@xilinx.com> wrote: >> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> >> >> Code is taken from Linux kernel driver. >> >> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> >> Signed-off-by: Michal Simek <michal.simek@xilinx.com> >> --- >> >> drivers/net/phy/Makefile | 1 + >> drivers/net/phy/phy.c | 3 + >> drivers/net/phy/ti.c | 205 +++++++++++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 209 insertions(+) >> create mode 100644 drivers/net/phy/ti.c >> >> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile >> index d096db87a276..9e4d4927e676 100644 >> --- a/drivers/net/phy/Makefile >> +++ b/drivers/net/phy/Makefile >> @@ -24,4 +24,5 @@ obj-$(CONFIG_PHY_NATSEMI) += natsemi.o >> obj-$(CONFIG_PHY_REALTEK) += realtek.o >> obj-$(CONFIG_PHY_SMSC) += smsc.o >> obj-$(CONFIG_PHY_TERANETICS) += teranetics.o >> +obj-$(CONFIG_PHY_TI) += ti.o >> obj-$(CONFIG_PHY_VITESSE) += vitesse.o >> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c >> index a6023f1033ec..c6046e4abc4e 100644 >> --- a/drivers/net/phy/phy.c >> +++ b/drivers/net/phy/phy.c >> @@ -484,6 +484,9 @@ int phy_init(void) >> #ifdef CONFIG_PHY_TERANETICS >> phy_teranetics_init(); >> #endif >> +#ifdef CONFIG_PHY_TI >> + phy_ti_init(); >> +#endif >> #ifdef CONFIG_PHY_VITESSE >> phy_vitesse_init(); >> #endif >> diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c >> new file mode 100644 >> index 000000000000..bb30450d7531 >> --- /dev/null >> +++ b/drivers/net/phy/ti.c >> @@ -0,0 +1,205 @@ >> +/* >> + * TI PHY drivers >> + * >> + * SPDX-License-Identifier: GPL-2.0 >> + * >> + */ >> +#include <common.h> >> +#include <phy.h> >> + >> +/* TI DP83867 */ >> +#define DP83867_DEVADDR 0x1f >> + >> +#define MII_DP83867_PHYCTRL 0x10 >> +#define MII_DP83867_MICR 0x12 >> +#define DP83867_CTRL 0x1f >> + >> +/* Extended Registers */ >> +#define DP83867_RGMIICTL 0x0032 >> +#define DP83867_RGMIIDCTL 0x0086 >> + >> +/* FIXME this is consolidated in the latest U-Boot version */ >> +#define BIT(x) (1UL << (x)) > > Indeed. Fixed in v2. > >> +#define DP83867_SW_RESET (1 << 15) >> +#define DP83867_SW_RESTART (1 << 14) >> + >> +/* MICR Interrupt bits */ >> +#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) >> +#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) >> +#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) >> +#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) >> +#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) >> +#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) >> +#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) >> +#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) >> +#define MII_DP83867_MICR_WOL_INT_EN BIT(3) >> +#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) >> +#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) >> +#define MII_DP83867_MICR_JABBER_INT_EN BIT(0) >> + >> +/* RGMIICTL bits */ >> +#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) >> +#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) >> + >> +/* PHY CTRL bits */ >> +#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 >> + >> +/* RGMIIDCTL bits */ >> +#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 >> + >> +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ >> +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ >> + >> +/* MMD Access Control register fields */ >> +#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ >> +#define MII_MMD_CTRL_ADDR 0x0000 /* Address */ >> +#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ >> +#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ >> +#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ >> + >> +/* FIXME: These indirect PHY writes should go into common code. */ > > By this comment, you mean common to this phy and other phys? > > Either fix or remove the comment. ok. I will remove this comment. We can move it when other drivers need it. > >> +/** >> + * phy_read_mmd_indirect - reads data from the MMD registers >> + * @phydev: The PHY device bus >> + * @prtad: MMD Address >> + * @devad: MMD DEVAD >> + * @addr: PHY address on the MII bus >> + * >> + * Description: it reads data from the MMD registers (clause 22 to access to >> + * clause 45) of the specified phy address. >> + * To read these register we have: > > register -> registers fixed. > >> + * 1) Write reg 13 // DEVAD >> + * 2) Write reg 14 // MMD Address >> + * 3) Write reg 13 // MMD Data Command for MMD DEVAD >> + * 3) Read reg 14 // Read MMD data >> + */ >> +int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, >> + int devad, int addr) >> +{ >> + int value = -1; >> + >> + /* Write the desired MMD Devad */ >> + phy_write(phydev, addr, MII_MMD_CTRL, devad); >> + >> + /* Write the desired MMD register address */ >> + phy_write(phydev, addr, MII_MMD_DATA, prtad); >> + >> + /* Select the Function : DATA with no post increment */ >> + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); >> + >> + /* Read the content of the MMD's selected register */ >> + value = phy_read(phydev, addr, MII_MMD_DATA); >> + return value; >> +} >> + >> +/** >> + * phy_write_mmd_indirect - writes data to the MMD registers >> + * @phydev: The PHY device >> + * @prtad: MMD Address >> + * @devad: MMD DEVAD >> + * @addr: PHY address on the MII bus >> + * @data: data to write in the MMD register >> + * >> + * Description: Write data from the MMD registers of the specified >> + * phy address. >> + * To write these register we have: fixed type here too Thanks, Michal
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index d096db87a276..9e4d4927e676 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -24,4 +24,5 @@ obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o +obj-$(CONFIG_PHY_TI) += ti.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index a6023f1033ec..c6046e4abc4e 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -484,6 +484,9 @@ int phy_init(void) #ifdef CONFIG_PHY_TERANETICS phy_teranetics_init(); #endif +#ifdef CONFIG_PHY_TI + phy_ti_init(); +#endif #ifdef CONFIG_PHY_VITESSE phy_vitesse_init(); #endif diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c new file mode 100644 index 000000000000..bb30450d7531 --- /dev/null +++ b/drivers/net/phy/ti.c @@ -0,0 +1,205 @@ +/* + * TI PHY drivers + * + * SPDX-License-Identifier: GPL-2.0 + * + */ +#include <common.h> +#include <phy.h> + +/* TI DP83867 */ +#define DP83867_DEVADDR 0x1f + +#define MII_DP83867_PHYCTRL 0x10 +#define MII_DP83867_MICR 0x12 +#define DP83867_CTRL 0x1f + +/* Extended Registers */ +#define DP83867_RGMIICTL 0x0032 +#define DP83867_RGMIIDCTL 0x0086 + +/* FIXME this is consolidated in the latest U-Boot version */ +#define BIT(x) (1UL << (x)) + +#define DP83867_SW_RESET (1 << 15) +#define DP83867_SW_RESTART (1 << 14) + +/* MICR Interrupt bits */ +#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) +#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) +#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) +#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) +#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) +#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) +#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) +#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) +#define MII_DP83867_MICR_WOL_INT_EN BIT(3) +#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) +#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) +#define MII_DP83867_MICR_JABBER_INT_EN BIT(0) + +/* RGMIICTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) +#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 + +/* RGMIIDCTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 + +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ + +/* MMD Access Control register fields */ +#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ +#define MII_MMD_CTRL_ADDR 0x0000 /* Address */ +#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ +#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ +#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ + +/* FIXME: These indirect PHY writes should go into common code. */ + +/** + * phy_read_mmd_indirect - reads data from the MMD registers + * @phydev: The PHY device bus + * @prtad: MMD Address + * @devad: MMD DEVAD + * @addr: PHY address on the MII bus + * + * Description: it reads data from the MMD registers (clause 22 to access to + * clause 45) of the specified phy address. + * To read these register we have: + * 1) Write reg 13 // DEVAD + * 2) Write reg 14 // MMD Address + * 3) Write reg 13 // MMD Data Command for MMD DEVAD + * 3) Read reg 14 // Read MMD data + */ +int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, + int devad, int addr) +{ + int value = -1; + + /* Write the desired MMD Devad */ + phy_write(phydev, addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, addr, MII_MMD_DATA, prtad); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); + + /* Read the content of the MMD's selected register */ + value = phy_read(phydev, addr, MII_MMD_DATA); + return value; +} + +/** + * phy_write_mmd_indirect - writes data to the MMD registers + * @phydev: The PHY device + * @prtad: MMD Address + * @devad: MMD DEVAD + * @addr: PHY address on the MII bus + * @data: data to write in the MMD register + * + * Description: Write data from the MMD registers of the specified + * phy address. + * To write these register we have: + * 1) Write reg 13 // DEVAD + * 2) Write reg 14 // MMD Address + * 3) Write reg 13 // MMD Data Command for MMD DEVAD + * 3) Write reg 14 // Write MMD data + */ +void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, + int devad, int addr, u32 data) +{ + /* Write the desired MMD Devad */ + phy_write(phydev, addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, addr, MII_MMD_DATA, prtad); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); + + /* Write the data into MMD's selected register */ + phy_write(phydev, addr, MII_MMD_DATA, data); +} + +/** + * phy_interface_is_rgmii - Convenience function for testing if a PHY interface + * is RGMII (all variants) + * @phydev: the phy_device struct + */ +static inline bool phy_interface_is_rgmii(struct phy_device *phydev) +{ + return phydev->interface >= PHY_INTERFACE_MODE_RGMII && + phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; +} + +/* User setting - can be taken from DTS */ +#define RX_ID_DELAY 8 +#define TX_ID_DELAY 0xa +#define FIFO_DEPTH 1 + +static int dp83867_config(struct phy_device *phydev) +{ + unsigned int val, delay; + int ret; + + /* Restart the PHY. */ + val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); + phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, + val | DP83867_SW_RESTART); + + if (phy_interface_is_rgmii(phydev)) { + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, + (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); + if (ret) + return ret; + } + + if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && + (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { + val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83867_RGMII_TX_CLK_DELAY_EN | + DP83867_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83867_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83867_RGMII_RX_CLK_DELAY_EN; + + phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr, val); + + delay = (RX_ID_DELAY | + (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); + + phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, + DP83867_DEVADDR, phydev->addr, delay); + } + + genphy_config_aneg(phydev); + return 0; +} + +static struct phy_driver DP83867_driver = { + .name = "TI DP83867", + .uid = 0x2000a231, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .config = &dp83867_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_ti_init(void) +{ + phy_register(&DP83867_driver); + return 0; +}