diff mbox

[U-Boot,v2] arm: socfpga: Add SoCFPGA SR1500 board

Message ID 1445848611-5632-1-git-send-email-sr@denx.de
State Superseded
Delegated to: Marek Vasut
Headers show

Commit Message

Stefan Roese Oct. 26, 2015, 8:36 a.m. UTC 
The SR1500 board is a CycloneV based board, similar to the EBV
SoCrates, equipped with the following devices:

- SPI NOR
- eMMC
- Ethernet

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
---
v2:
- Addressed various review comments from Marek:
- Added chapter about SPL integration for SoC FPGA in doc/README.socfpga
- Delay after PHY reset deassertion added
- Reshuffle of the code for the PHY test code (fixes and cleanup)
- Cleanup of the board config header

 arch/arm/dts/Makefile                    |   4 +-
 arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +++++
 arch/arm/mach-socfpga/Kconfig            |   6 +
 board/sr1500/MAINTAINERS                 |   6 +
 board/sr1500/Makefile                    |   7 +
 board/sr1500/qts/iocsr_config.h          | 660 +++++++++++++++++++++++++++++++
 board/sr1500/qts/pinmux_config.h         | 219 ++++++++++
 board/sr1500/qts/pll_config.h            |  85 ++++
 board/sr1500/qts/sdram_config.h          | 341 ++++++++++++++++
 board/sr1500/socfpga.c                   | 151 +++++++
 configs/socfpga_sr1500_defconfig         |  17 +
 doc/README.socfpga                       |  74 +++-
 include/configs/socfpga_sr1500.h         | 113 ++++++
 13 files changed, 1782 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts
 create mode 100644 board/sr1500/MAINTAINERS
 create mode 100644 board/sr1500/Makefile
 create mode 100644 board/sr1500/qts/iocsr_config.h
 create mode 100644 board/sr1500/qts/pinmux_config.h
 create mode 100644 board/sr1500/qts/pll_config.h
 create mode 100644 board/sr1500/qts/sdram_config.h
 create mode 100644 board/sr1500/socfpga.c
 create mode 100644 configs/socfpga_sr1500_defconfig
 create mode 100644 include/configs/socfpga_sr1500.h

Comments

Dinh Nguyen Oct. 27, 2015, 3:29 p.m. UTC | #1 
Hi Stefan,

On 10/26/2015 03:36 AM, Stefan Roese wrote:
> The SR1500 board is a CycloneV based board, similar to the EBV
> SoCrates, equipped with the following devices:
> 
> - SPI NOR
> - eMMC
> - Ethernet
> 
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Pavel Machek <pavel@denx.de>
> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> ---
> v2:
> - Addressed various review comments from Marek:
> - Added chapter about SPL integration for SoC FPGA in doc/README.socfpga
> - Delay after PHY reset deassertion added
> - Reshuffle of the code for the PHY test code (fixes and cleanup)
> - Cleanup of the board config header
> 
>  arch/arm/dts/Makefile                    |   4 +-
>  arch/arm/dts/socfpga_cyclone5_sr1500.dts | 101 +++++
>  arch/arm/mach-socfpga/Kconfig            |   6 +
>  board/sr1500/MAINTAINERS                 |   6 +
>  board/sr1500/Makefile                    |   7 +
>  board/sr1500/qts/iocsr_config.h          | 660 +++++++++++++++++++++++++++++++
>  board/sr1500/qts/pinmux_config.h         | 219 ++++++++++
>  board/sr1500/qts/pll_config.h            |  85 ++++
>  board/sr1500/qts/sdram_config.h          | 341 ++++++++++++++++
>  board/sr1500/socfpga.c                   | 151 +++++++
>  configs/socfpga_sr1500_defconfig         |  17 +
>  doc/README.socfpga                       |  74 +++-
>  include/configs/socfpga_sr1500.h         | 113 ++++++
>  13 files changed, 1782 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/dts/socfpga_cyclone5_sr1500.dts
>  create mode 100644 board/sr1500/MAINTAINERS
>  create mode 100644 board/sr1500/Makefile
>  create mode 100644 board/sr1500/qts/iocsr_config.h
>  create mode 100644 board/sr1500/qts/pinmux_config.h
>  create mode 100644 board/sr1500/qts/pll_config.h
>  create mode 100644 board/sr1500/qts/sdram_config.h
>  create mode 100644 board/sr1500/socfpga.c
>  create mode 100644 configs/socfpga_sr1500_defconfig
>  create mode 100644 include/configs/socfpga_sr1500.h
> 


> diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
> new file mode 100644
> index 0000000..def01fb
> --- /dev/null
> +++ b/include/configs/socfpga_sr1500.h
> @@ -0,0 +1,113 @@
> +/*
> + * Copyright (C) 2015 Stefan Roese <sr@denx.de>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +#ifndef __CONFIG_SOCFPGA_SR1500_H__
> +#define __CONFIG_SOCFPGA_SR1500_H__
> +
> +#include <asm/arch/socfpga_base_addrs.h>
> +
> +#define CONFIG_BOARD_EARLY_INIT_F
> +
> +#define CONFIG_SYS_NO_FLASH
> +#define CONFIG_DOS_PARTITION
> +#define CONFIG_FAT_WRITE
> +
> +#define CONFIG_HW_WATCHDOG
> +
> +/* U-Boot Commands */
> +#define CONFIG_CMD_ASKENV
> +#define CONFIG_CMD_BOOTZ
> +#define CONFIG_CMD_CACHE
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_EXT4
> +#define CONFIG_CMD_EXT4_WRITE
> +#define CONFIG_CMD_FAT
> +#define CONFIG_CMD_FS_GENERIC
> +#define CONFIG_CMD_GPIO
> +#define CONFIG_CMD_GREPENV
> +#define CONFIG_CMD_MEMTEST
> +#define CONFIG_CMD_MII
> +#define CONFIG_CMD_MMC
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_SF
> +#define CONFIG_CMD_SPI
> +#define CONFIG_CMD_TIME
> +
> +/* Memory configurations */
> +#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */
> +
> +/* Booting Linux */
> +#define CONFIG_BOOTDELAY	3
> +#define CONFIG_BOOTFILE		"uImage"
> +#define CONFIG_BOOTARGS		"console=ttyS0" __stringify(CONFIG_BAUDRATE)
> +#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
> +#define CONFIG_LOADADDR		0x8000

All of the other boards have switched to use 0x01000000 as the LOADADDR.

Dinh
Marek Vasut Oct. 28, 2015, 5:45 p.m. UTC | #2 
On Monday, October 26, 2015 at 09:36:51 AM, Stefan Roese wrote:

Hi!

[...]

> diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c
> new file mode 100644
> index 0000000..35d68a9
> --- /dev/null
> +++ b/board/sr1500/socfpga.c
> @@ -0,0 +1,151 @@
> +/*
> + * Copyright (C) 2015 Stefan Roese <sr@denx.de>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <i2c.h>
> +#include <miiphy.h>
> +#include <asm/arch/reset_manager.h>
> +#include <asm/gpio.h>
> +#include <asm/io.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +void s_init(void) {}
> +
> +/*
> + * Miscellaneous platform dependent initialisations
> + */
> +int board_init(void)
> +{
> +	/* Address of boot parameters for ATAG (if ATAG is used) */
> +	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
> +
> +	return 0;
> +}
> +
> +int board_early_init_f(void)
> +{
> +	int ret;
> +
> +	/* Reset the Marvell PHY 88E1510 */
> +	ret = gpio_request(63, "PHY reset");
> +	if (ret)
> +		return ret;
> +
> +	gpio_direction_output(63, 0);
> +	mdelay(10);
> +	gpio_set_value(63, 1);
> +	mdelay(10);
> +
> +	return 0;
> +}
> +
> +#define CONFIG_SYS_IDT_CLK_ADDR		0x6a
> +
> +static int do_clksave(cmd_tbl_t *cmdtp, int flag, int argc, char *const
> argv[]) +{
> +	u8 buf[1];

u8 buf = 0x1;

i2c_write(....., &buf, 1);

this would work too.

> +	buf[0] = 0x01;
> +	i2c_write(CONFIG_SYS_IDT_CLK_ADDR, 0, 0, buf, 1);
> +
> +	return 0;
> +}
> +
> +U_BOOT_CMD(clksave, 1, 0, do_clksave,
> +	   "IDT 5V49EE702 Progsave command", "");

Every time you do this in a board file, a kitten dies :-(

[...]

> +static int do_phytest(cmd_tbl_t *cmdtp, int flag, int argc, char *const
> argv[]) +{
> +	const char devname[] = NET_DEV_NAME;
> +	unsigned long ts;
> +	char str[32];
> +	u8 addr = 0;
> +	u16 data;
> +	u16 status;
> +	u16 oldpage;
> +	int i;
> +
> +	/* Save current page register */
> +	miiphy_read(devname, addr, MII_MARVELL_PHY_PAGE, &oldpage);
> +
> +	/*
> +	 * Run cable disgnostics
> +	 */
> +	printf("Running cable diagnostic test...");
> +	miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, 7);
> +	miiphy_write(devname, addr, 21, PHY_DIAG_START);
> +
> +	ts = get_timer(0);
> +	do {
> +		miiphy_read(devname, addr, 21, &data);

miiphy_read() can also return an error code I think, in which case $data
would be invalid. Right ?

> +		if ((data & PHY_DIAG_BUSY) != PHY_DIAG_BUSY)
> +			break;
> +
> +		mdelay(1);
> +	} while (get_timer(ts) < PHY_DIAG_TIMEOUT);
> +	printf("done!\n");
> +
> +	miiphy_read(devname, addr, 20, &status);
> +
> +	for (i = 0; i < 4; i++) {
> +		int val;
> +
> +		val = (status >> (i * 4)) & 0x000f;
> +		pair_state(val, str);
> +		printf("Pair %d: %s", i, str);
> +
> +		/* Only print fault length if not okay */
> +		if (val != 0x01) {
> +			miiphy_read(devname, addr, 16 + i, &data);
> +			printf(" - Length to fault %d cm", data);
> +		}
> +		printf("\n");
> +	}
> +
> +	/* Restore original page */
> +	miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, oldpage);
> +
> +	return 0;
> +}
> +
> +U_BOOT_CMD(phytest, 1, 1, do_phytest,
> +	   "Marvell PHY test command - dump some values", "");

And yet another kitten down ;-)

[...]

> diff --git a/doc/README.socfpga b/doc/README.socfpga

Please , put this README into a separate patch :-(

> index cfcbbfe..eebf373 100644
> --- a/doc/README.socfpga
> +++ b/doc/README.socfpga
> @@ -7,7 +7,6 @@ This README is about U-Boot and SPL support for Altera's
> ARM Cortex-A9MPCore based SOCFPGA. To know more about the hardware itself,
> please refer to www.altera.com.
> 
> -
>  --------------------------------------------
>  socfpga_dw_mmc
>  --------------------------------------------
> @@ -51,3 +50,76 @@ the card
>  #define CONFIG_SOCFPGA_DWMMC_BUS_HZ	50000000
>  -> The clock rate to controller. Do note the controller have a wrapper
> which divide the clock from PLL by 4.
> +
> +-------------------------------------------------------------------------
> +Generating the header files for SPL intergration as a replacement for the
> +Preloader
> +-------------------------------------------------------------------------
> +This text assumes the use of Quartus 14.0.200
> +
> +I) Rebuilding the MCVEVK Quartus project

This is not MCV-specific ;-)

> +----------------------------------------
> + 1) Navigate to DENX_MCV_reference_* directory
> + 2) Run Quartus II
> + 3) Open Project (Ctrl+J), select DENX_MCV_reference.qpf
> + 4) Run QSys [Tools->QSys]
> +    4.1) In the Open dialog, select 'mcv_hps.qsys'
> +    4.2) In the Open System dialog, wait until completion and press
> 'Close' +    4.3) In the Qsys window, click on 'Generate HDL...' in bottom
> right corner +         4.3.1) In the 'Generation' window, click 'Generate'
> +	 4.3.2) In the 'Generate' dialog, wait until completion and click 
'Close'
> +    4.4) In the QSys window, click 'Finish'
> +         4.4.1) In the 'Quartus II' pop up window, click 'OK'
> + 5) Back in Quartus II main window, do the following
> +    5.1) Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K)
> +    5.2) Use Processing -> Start Compilation (Ctrl+L)
> +    ... have lunch, coffee, play games ...
> +
> + [
> +   NOTE: Steps 2-5 above can be also done using a convenience scripts
> +         from the command line:
> +	 $ ./qsys.sh && ./anal.sh && ./build.sh

This is definitelly NOT standard . Please drop this NOTE altogether.

You can use something like the following to compile the quartus project,
which is standard way to do it (that replaces that anal.sh and build.sh
scripts):

$ quartus_sh --flow compile <project>

To generate the qsys system (replacement for qsys.sh), hrm, I guess you
should use "ip-generate", but that takes many options. Dinh, is there some
magic invocation for ip-generate which takes the qsys file and generates
the system ?

> + ]
> +
> + 6) Launch a separate terminal window
> +    6.1) Change directory to 'software/spl_bsp'
> +    6.2) Export path to embedded command shell and friends
> +         $ export PATH=/work/DENX/Altera/Quartus/14.0/embedded/:$PATH

14.0 should be replaced by 15.0 ;-)

> +    6.3) Start embedded command shell (ECS)
> +         $ embedded_command_shell.sh
> +    6.4) Prepare BSP by launching the BSP editor from ECS
> +         => bsp-editor
> +    6.5) In BSP editor
> +         6.5.1) Use File -> Open
> +	 6.5.2) Select 'settings.bsp' file
> +	 6.5.4) Click Generate
> +	 6.5.5) Click Exit
> +
> +Now the necessary files are generated. And U-Boot can be used
> +to generate the SPL header files. For this, please use the
> +following script:
> +
> +./arch/arm/mach-socfpga/qts-filter.sh cyclone5 \
> +	/path/to/quartus/project /path/to/output/qts/
> +
> +This will generate the following 4 files:
> +
> +iocsr_config.h
> +pinmux_config.h
> +pll_config.h
> +sdram_config.h
> +
> +These files need to be copied into "qts" directory in the board
> +directory. Here the example for the DENX MCVEVK:
> +
> +$ ll board/denx/mcvevk/qts/
> +total 44
> +drwxrwxr-x 2 stefan stefan 4096 Okt 20 07:07 ./
> +drwxrwxr-x 3 stefan stefan 4096 Okt 21 13:06 ../
> +-rw-rw-r-- 1 stefan stefan 8826 Okt 20 07:07 iocsr_config.h
> +-rw-rw-r-- 1 stefan stefan 4398 Okt 20 07:07 pinmux_config.h
> +-rw-rw-r-- 1 stefan stefan 3192 Okt 20 07:07 pll_config.h
> +-rw-rw-r-- 1 stefan stefan 9031 Okt 20 07:07 sdram_config.h

Oct please ;-)

> +Now you board is ready for full mainline support including
> +U-Boot SPL. The Preloader will not be needed any more.

... is not needed ... 

[...]
diff mbox

Patch

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index ddc6a05..b77aab48 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -74,7 +74,9 @@  dtb-$(CONFIG_ARCH_SOCFPGA) +=				\
 	socfpga_cyclone5_socdk.dtb			\
 	socfpga_cyclone5_de0_nano_soc.dtb			\
 	socfpga_cyclone5_sockit.dtb			\
-	socfpga_cyclone5_socrates.dtb
+	socfpga_cyclone5_socrates.dtb			\
+	socfpga_cyclone5_sr1500.dtb
+
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb
 dtb-$(CONFIG_TARGET_BEAGLE_X15) += am57xx-beagle-x15.dtb
 dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
new file mode 100644
index 0000000..3729ca0
--- /dev/null
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -0,0 +1,101 @@ 
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include "socfpga_cyclone5.dtsi"
+
+/ {
+	model = "SoCFPGA Cyclone V SR1500";
+	compatible = "anonymous,socfpga-sr1500", "altr,socfpga-cyclone5", "altr,socfpga";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	aliases {
+		/*
+		 * This allows the ethaddr uboot environmnet variable
+		 * contents to be added to the gmac1 device tree blob.
+		 */
+		ethernet0 = &gmac1;
+	};
+
+	memory@0 {
+		name = "memory";
+		device_type = "memory";
+		reg = <0x0 0x40000000>; /* 1GB */
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&gmac1 {
+	status = "okay";
+	phy-mode = "rgmii";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	speed-mode = <0>;
+};
+
+&i2c1 {
+	status = "okay";
+	speed-mode = <0>;
+};
+
+&mmc0 {
+	status = "okay";
+	bus-width = <8>;
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb1 {
+	status = "okay";
+};
+
+&watchdog0 {
+	status = "okay";
+};
+
+&qspi {
+	status = "okay";
+	u-boot,dm-pre-reloc;
+
+	flash0: n25q00@0 {
+		u-boot,dm-pre-reloc;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "n25q00", "spi-flash";
+		reg = <0>;      /* chip select */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		page-size = <256>;
+		block-size = <16>; /* 2^16, 64KB */
+		read-delay = <4>;  /* delay value in read data capture register */
+		tshsl-ns = <50>;
+		tsd2d-ns = <50>;
+		tchsh-ns = <4>;
+		tslch-ns = <4>;
+	};
+};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index a413ea4..aa12df2 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -22,6 +22,10 @@  config TARGET_SOCFPGA_DENX_MCVEVK
 	bool "DENX MCVEVK (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
 
+config TARGET_SOCFPGA_SR1500
+	bool "SR1500 (Cyclone V)"
+	select TARGET_SOCFPGA_CYCLONE5
+
 config TARGET_SOCFPGA_TERASIC_DE0_NANO
 	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
 	select TARGET_SOCFPGA_CYCLONE5
@@ -38,6 +42,7 @@  config SYS_BOARD
 	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "sr1500" if TARGET_SOCFPGA_SR1500
 
 config SYS_VENDOR
 	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
@@ -55,5 +60,6 @@  config SYS_CONFIG_NAME
 	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
 	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
 	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
+	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
 
 endif
diff --git a/board/sr1500/MAINTAINERS b/board/sr1500/MAINTAINERS
new file mode 100644
index 0000000..ed013a8
--- /dev/null
+++ b/board/sr1500/MAINTAINERS
@@ -0,0 +1,6 @@ 
+SOCFPGA SR1500 BOARD
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/sr1500/
+F:	include/configs/socfpga_sr1500.h
+F:	configs/socfpga_sr1500_defconfig
diff --git a/board/sr1500/Makefile b/board/sr1500/Makefile
new file mode 100644
index 0000000..eae7ad0
--- /dev/null
+++ b/board/sr1500/Makefile
@@ -0,0 +1,7 @@ 
+#
+# Copyright (C) 2015 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	:= socfpga.o
diff --git a/board/sr1500/qts/iocsr_config.h b/board/sr1500/qts/iocsr_config.h
new file mode 100644
index 0000000..aa1e65c
--- /dev/null
+++ b/board/sr1500/qts/iocsr_config.h
@@ -0,0 +1,660 @@ 
+/*
+ * Altera SoCFPGA IOCSR configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_IOCSR_CONFIG_H__
+#define __SOCFPGA_IOCSR_CONFIG_H__
+
+#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH	764
+#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH	1719
+#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH	955
+#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH	16766
+
+const unsigned long iocsr_scan_chain0_table[] = {
+	0x00100000,
+	0x40000000,
+	0x0FF00000,
+	0xC0000000,
+	0x0000003F,
+	0x00008000,
+	0x000E0180,
+	0x18060000,
+	0x18000000,
+	0x00018060,
+	0x00020000,
+	0x00004000,
+	0x000700C0,
+	0x1C030000,
+	0x0C000000,
+	0x00000070,
+	0x0001C030,
+	0x00002000,
+	0x00018060,
+	0x0E018000,
+	0x06000000,
+	0x00000038,
+	0x0000E018,
+	0x00001000,
+};
+
+const unsigned long iocsr_scan_chain1_table[] = {
+	0x001C0300,
+	0x300C0000,
+	0x300000C0,
+	0x000000C0,
+	0x000300C0,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x000000E0,
+	0x00018060,
+	0x00004000,
+	0x000300C0,
+	0x1C030000,
+	0x0C000000,
+	0x00000030,
+	0x0000C030,
+	0x00002000,
+	0x06018060,
+	0x06018000,
+	0x01FE0000,
+	0xF8000000,
+	0x00000007,
+	0x00001000,
+	0x0000C030,
+	0x0300C000,
+	0x03000000,
+	0x0000300C,
+	0x0000300C,
+	0x00000800,
+	0x00000000,
+	0x00000000,
+	0x01800000,
+	0x00000006,
+	0x00001806,
+	0x00000400,
+	0x00000000,
+	0x00C03000,
+	0x00000003,
+	0x00000000,
+	0x00000000,
+	0x00000200,
+	0x00601806,
+	0x00000000,
+	0x80600000,
+	0x80000601,
+	0x00000601,
+	0x00000100,
+	0x00300C03,
+	0xC0300C00,
+	0xC0300000,
+	0xC0000300,
+	0x000C0300,
+	0x00000080,
+};
+
+const unsigned long iocsr_scan_chain2_table[] = {
+	0x000C0300,
+	0x700C0000,
+	0x0FF00000,
+	0x00000000,
+	0x000700C0,
+	0x00008000,
+	0x00060180,
+	0x18060000,
+	0x18000000,
+	0x00000060,
+	0x00018060,
+	0x00004000,
+	0x200300C0,
+	0x0C030000,
+	0x0C000000,
+	0x00000070,
+	0x0001C030,
+	0x00002000,
+	0x10018060,
+	0x0E018000,
+	0x06000000,
+	0x00010018,
+	0x0000E018,
+	0x00001000,
+	0x0001C030,
+	0x04000000,
+	0x03000000,
+	0x0000800C,
+	0x00C0300C,
+	0x00000800,
+};
+
+const unsigned long iocsr_scan_chain3_table[] = {
+	0x0C420D80,
+	0x0C3000FF,
+	0x0A804001,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x20430000,
+	0x0C003001,
+	0x00C00481,
+	0x00000000,
+	0x00000021,
+	0x82000004,
+	0x05400000,
+	0x03C80000,
+	0x04010000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x90218000,
+	0x86001800,
+	0x00600240,
+	0x80090218,
+	0x00000001,
+	0x40000002,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4810C000,
+	0x43000C00,
+	0x00300120,
+	0xC004810C,
+	0x12043000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x806180D0,
+	0x34071C06,
+	0x01A034D0,
+	0x180D0000,
+	0x71C06806,
+	0x01450340,
+	0xD000001A,
+	0x0680E380,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x18000000,
+	0x01800902,
+	0x00240860,
+	0x007F8006,
+	0x00000000,
+	0x0A800001,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x0A800000,
+	0x07900000,
+	0x08020000,
+	0x00100000,
+	0x20430000,
+	0x0C003001,
+	0x00C00481,
+	0x00000FF0,
+	0x4810C000,
+	0x80000C00,
+	0x05400000,
+	0x02480000,
+	0x04000000,
+	0x00080000,
+	0x05400000,
+	0x03C80000,
+	0x05400000,
+	0x03C80000,
+	0x90218000,
+	0x86001800,
+	0x00600240,
+	0x80090218,
+	0x24086001,
+	0x40000600,
+	0x02A00040,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x02A00000,
+	0x01E40000,
+	0x4810C000,
+	0x43000C00,
+	0x00300120,
+	0xC004810C,
+	0x12043000,
+	0x20000300,
+	0x00040000,
+	0x50670000,
+	0x00000010,
+	0x24590000,
+	0x00001000,
+	0xA0000034,
+	0x0D000001,
+	0xC0680618,
+	0x45034071,
+	0x0A281A01,
+	0x80E380D0,
+	0x34071C06,
+	0x01A00040,
+	0x180D0002,
+	0x71C06806,
+	0x01450340,
+	0xD00A281A,
+	0x06806180,
+	0x10040000,
+	0x00200000,
+	0x10040000,
+	0x00200000,
+	0x15000000,
+	0x0F200000,
+	0x15000000,
+	0x0F200000,
+	0x01FE0000,
+	0x18000000,
+	0x01800902,
+	0x00240860,
+	0x007F8006,
+	0x00000000,
+	0x99300001,
+	0x34343400,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040100,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x01000000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x2043090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00002000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xCB2CA3DD,
+	0xF5D5551E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x030C0680,
+	0xDD59647A,
+	0x1ECB2CA3,
+	0x48F5D555,
+	0x00035AD3,
+	0x00080000,
+	0x00001000,
+	0x00080200,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x00003FC2,
+	0x00820000,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00808000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020080,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00000010,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00015000,
+	0x0000F200,
+	0x00000000,
+	0x00000482,
+	0x86120800,
+	0x00600240,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xCB2CA3DD,
+	0xF5D9651E,
+	0x035AB2C8,
+	0x821A0041,
+	0x0000D000,
+	0x00000680,
+	0xDD59647A,
+	0x1ECB2CA3,
+	0x48F5D965,
+	0x00035AD3,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x10000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820004,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00808000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x0002A000,
+	0x0001E400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x2043090C,
+	0x00003001,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010000,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00202000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F3690D,
+	0x1A041414,
+	0x00D00000,
+	0x14864000,
+	0x59647A05,
+	0xCB2CA3D5,
+	0xF6D9651E,
+	0x035AB2C8,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xDD59647A,
+	0x1ECB2CA3,
+	0x48F5D965,
+	0x00034AD3,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x04000002,
+	0x00820004,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0xAA0D4000,
+	0x01C3A800,
+	0x00040000,
+	0x00000800,
+	0x00000000,
+	0x00001208,
+	0x00482000,
+	0x00800000,
+	0x00000000,
+	0x00410482,
+	0x0006A000,
+	0x0001B400,
+	0x00020000,
+	0x00000400,
+	0x00020000,
+	0x00000400,
+	0x5506A000,
+	0x00E1D400,
+	0x00000000,
+	0x0000090C,
+	0x00001000,
+	0x90400000,
+	0x00000000,
+	0x2020C243,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x2A835000,
+	0x0070EA00,
+	0x00010040,
+	0x00000200,
+	0x00000000,
+	0x00000482,
+	0x00120800,
+	0x00400000,
+	0x80000000,
+	0x00104120,
+	0x00000200,
+	0xAC0D5F80,
+	0xFFFFFFFF,
+	0x14F1690D,
+	0x1A041414,
+	0x00D00000,
+	0x04864000,
+	0x69A47A01,
+	0xCB2CA3D5,
+	0xF6D9651E,
+	0x034AD348,
+	0x821A0000,
+	0x0000D000,
+	0x00000680,
+	0xD559647A,
+	0x1ECB2CA3,
+	0x48F6D965,
+	0x00034A92,
+	0x00080000,
+	0x00001000,
+	0x00080000,
+	0x00001000,
+	0x000A8000,
+	0x00075000,
+	0x541A8000,
+	0x03875001,
+	0x00000000,
+	0x00000010,
+	0x0080C000,
+	0x41000000,
+	0x00000002,
+	0x00820004,
+	0x00489800,
+	0x801A1A1A,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x80000004,
+	0x00000200,
+	0x00000004,
+	0x00000200,
+	0x00000004,
+	0x00040000,
+	0x10000000,
+	0x00000000,
+	0x00004000,
+	0x00010000,
+	0x40002080,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00000100,
+	0x40000002,
+	0x00000100,
+	0x00000002,
+	0x00020000,
+	0x08000000,
+	0x00000008,
+	0x00000020,
+	0x00008000,
+	0x20001040,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x20000001,
+	0x00000080,
+	0x00000001,
+	0x00010000,
+	0x04000000,
+	0x00FF0000,
+	0x00000000,
+	0x00004000,
+	0x00000800,
+	0xC0000001,
+	0x00041419,
+	0x40000000,
+	0x04000816,
+	0x000D0000,
+	0x00006800,
+	0x00000340,
+	0xD000001A,
+	0x06800000,
+	0x00340000,
+	0x0001A000,
+	0x00000D00,
+	0x40000068,
+	0x1A000003,
+	0x00D00000,
+	0x00068000,
+	0x00003400,
+	0x000001A0,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x00000008,
+	0x00000401,
+	0x80000008,
+	0x0000007F,
+	0x20000000,
+	0x00000000,
+	0xE0000080,
+	0x0000001F,
+	0x00004000,
+};
+
+
+#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
diff --git a/board/sr1500/qts/pinmux_config.h b/board/sr1500/qts/pinmux_config.h
new file mode 100644
index 0000000..45e390d
--- /dev/null
+++ b/board/sr1500/qts/pinmux_config.h
@@ -0,0 +1,219 @@ 
+/*
+ * Altera SoCFPGA PinMux configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PINMUX_CONFIG_H__
+#define __SOCFPGA_PINMUX_CONFIG_H__
+
+const u8 sys_mgr_init_table[] = {
+	0, /* EMACIO0 */
+	2, /* EMACIO1 */
+	2, /* EMACIO2 */
+	2, /* EMACIO3 */
+	2, /* EMACIO4 */
+	2, /* EMACIO5 */
+	2, /* EMACIO6 */
+	2, /* EMACIO7 */
+	2, /* EMACIO8 */
+	0, /* EMACIO9 */
+	2, /* EMACIO10 */
+	2, /* EMACIO11 */
+	2, /* EMACIO12 */
+	2, /* EMACIO13 */
+	0, /* EMACIO14 */
+	0, /* EMACIO15 */
+	0, /* EMACIO16 */
+	0, /* EMACIO17 */
+	0, /* EMACIO18 */
+	0, /* EMACIO19 */
+	3, /* FLASHIO0 */
+	0, /* FLASHIO1 */
+	3, /* FLASHIO2 */
+	3, /* FLASHIO3 */
+	0, /* FLASHIO4 */
+	0, /* FLASHIO5 */
+	0, /* FLASHIO6 */
+	0, /* FLASHIO7 */
+	0, /* FLASHIO8 */
+	3, /* FLASHIO9 */
+	3, /* FLASHIO10 */
+	3, /* FLASHIO11 */
+	0, /* GENERALIO0 */
+	1, /* GENERALIO1 */
+	1, /* GENERALIO2 */
+	1, /* GENERALIO3 */
+	1, /* GENERALIO4 */
+	0, /* GENERALIO5 */
+	0, /* GENERALIO6 */
+	1, /* GENERALIO7 */
+	1, /* GENERALIO8 */
+	0, /* GENERALIO9 */
+	0, /* GENERALIO10 */
+	0, /* GENERALIO11 */
+	0, /* GENERALIO12 */
+	0, /* GENERALIO13 */
+	0, /* GENERALIO14 */
+	0, /* GENERALIO15 */
+	0, /* GENERALIO16 */
+	0, /* GENERALIO17 */
+	0, /* GENERALIO18 */
+	0, /* GENERALIO19 */
+	0, /* GENERALIO20 */
+	0, /* GENERALIO21 */
+	0, /* GENERALIO22 */
+	0, /* GENERALIO23 */
+	0, /* GENERALIO24 */
+	0, /* GENERALIO25 */
+	0, /* GENERALIO26 */
+	0, /* GENERALIO27 */
+	0, /* GENERALIO28 */
+	0, /* GENERALIO29 */
+	0, /* GENERALIO30 */
+	0, /* GENERALIO31 */
+	2, /* MIXED1IO0 */
+	2, /* MIXED1IO1 */
+	2, /* MIXED1IO2 */
+	2, /* MIXED1IO3 */
+	2, /* MIXED1IO4 */
+	2, /* MIXED1IO5 */
+	2, /* MIXED1IO6 */
+	2, /* MIXED1IO7 */
+	2, /* MIXED1IO8 */
+	2, /* MIXED1IO9 */
+	2, /* MIXED1IO10 */
+	2, /* MIXED1IO11 */
+	2, /* MIXED1IO12 */
+	2, /* MIXED1IO13 */
+	0, /* MIXED1IO14 */
+	3, /* MIXED1IO15 */
+	3, /* MIXED1IO16 */
+	3, /* MIXED1IO17 */
+	3, /* MIXED1IO18 */
+	3, /* MIXED1IO19 */
+	3, /* MIXED1IO20 */
+	0, /* MIXED1IO21 */
+	0, /* MIXED2IO0 */
+	0, /* MIXED2IO1 */
+	0, /* MIXED2IO2 */
+	0, /* MIXED2IO3 */
+	0, /* MIXED2IO4 */
+	0, /* MIXED2IO5 */
+	0, /* MIXED2IO6 */
+	0, /* MIXED2IO7 */
+	0, /* GPLINMUX48 */
+	0, /* GPLINMUX49 */
+	0, /* GPLINMUX50 */
+	0, /* GPLINMUX51 */
+	0, /* GPLINMUX52 */
+	0, /* GPLINMUX53 */
+	0, /* GPLINMUX54 */
+	0, /* GPLINMUX55 */
+	0, /* GPLINMUX56 */
+	0, /* GPLINMUX57 */
+	0, /* GPLINMUX58 */
+	0, /* GPLINMUX59 */
+	0, /* GPLINMUX60 */
+	0, /* GPLINMUX61 */
+	0, /* GPLINMUX62 */
+	0, /* GPLINMUX63 */
+	0, /* GPLINMUX64 */
+	0, /* GPLINMUX65 */
+	0, /* GPLINMUX66 */
+	0, /* GPLINMUX67 */
+	0, /* GPLINMUX68 */
+	0, /* GPLINMUX69 */
+	0, /* GPLINMUX70 */
+	0, /* GPLMUX0 */
+	1, /* GPLMUX1 */
+	1, /* GPLMUX2 */
+	1, /* GPLMUX3 */
+	1, /* GPLMUX4 */
+	1, /* GPLMUX5 */
+	1, /* GPLMUX6 */
+	1, /* GPLMUX7 */
+	1, /* GPLMUX8 */
+	0, /* GPLMUX9 */
+	1, /* GPLMUX10 */
+	1, /* GPLMUX11 */
+	1, /* GPLMUX12 */
+	1, /* GPLMUX13 */
+	1, /* GPLMUX14 */
+	1, /* GPLMUX15 */
+	1, /* GPLMUX16 */
+	1, /* GPLMUX17 */
+	1, /* GPLMUX18 */
+	1, /* GPLMUX19 */
+	1, /* GPLMUX20 */
+	1, /* GPLMUX21 */
+	1, /* GPLMUX22 */
+	1, /* GPLMUX23 */
+	1, /* GPLMUX24 */
+	1, /* GPLMUX25 */
+	1, /* GPLMUX26 */
+	1, /* GPLMUX27 */
+	0, /* GPLMUX28 */
+	1, /* GPLMUX29 */
+	1, /* GPLMUX30 */
+	1, /* GPLMUX31 */
+	1, /* GPLMUX32 */
+	1, /* GPLMUX33 */
+	1, /* GPLMUX34 */
+	0, /* GPLMUX35 */
+	1, /* GPLMUX36 */
+	0, /* GPLMUX37 */
+	1, /* GPLMUX38 */
+	1, /* GPLMUX39 */
+	0, /* GPLMUX40 */
+	0, /* GPLMUX41 */
+	0, /* GPLMUX42 */
+	0, /* GPLMUX43 */
+	0, /* GPLMUX44 */
+	1, /* GPLMUX45 */
+	1, /* GPLMUX46 */
+	1, /* GPLMUX47 */
+	0, /* GPLMUX48 */
+	1, /* GPLMUX49 */
+	1, /* GPLMUX50 */
+	1, /* GPLMUX51 */
+	1, /* GPLMUX52 */
+	0, /* GPLMUX53 */
+	0, /* GPLMUX54 */
+	1, /* GPLMUX55 */
+	1, /* GPLMUX56 */
+	0, /* GPLMUX57 */
+	0, /* GPLMUX58 */
+	0, /* GPLMUX59 */
+	0, /* GPLMUX60 */
+	0, /* GPLMUX61 */
+	0, /* GPLMUX62 */
+	1, /* GPLMUX63 */
+	1, /* GPLMUX64 */
+	1, /* GPLMUX65 */
+	1, /* GPLMUX66 */
+	1, /* GPLMUX67 */
+	1, /* GPLMUX68 */
+	1, /* GPLMUX69 */
+	1, /* GPLMUX70 */
+	0, /* NANDUSEFPGA */
+	0, /* UART0USEFPGA */
+	0, /* RGMII1USEFPGA */
+	0, /* SPIS0USEFPGA */
+	0, /* CAN0USEFPGA */
+	0, /* I2C0USEFPGA */
+	0, /* SDMMCUSEFPGA */
+	0, /* QSPIUSEFPGA */
+	0, /* SPIS1USEFPGA */
+	0, /* RGMII0USEFPGA */
+	0, /* UART1USEFPGA */
+	0, /* CAN1USEFPGA */
+	0, /* USB1USEFPGA */
+	0, /* I2C3USEFPGA */
+	0, /* I2C2USEFPGA */
+	0, /* I2C1USEFPGA */
+	0, /* SPIM1USEFPGA */
+	0, /* USB0USEFPGA */
+	0 /* SPIM0USEFPGA */
+};
+#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
diff --git a/board/sr1500/qts/pll_config.h b/board/sr1500/qts/pll_config.h
new file mode 100644
index 0000000..359e7ad
--- /dev/null
+++ b/board/sr1500/qts/pll_config.h
@@ -0,0 +1,85 @@ 
+/*
+ * Altera SoCFPGA Clock and PLL configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_PLL_CONFIG_H__
+#define __SOCFPGA_PLL_CONFIG_H__
+
+#define CONFIG_HPS_DBCTRL_STAYOSC1 1
+
+#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63
+#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
+#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
+#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
+#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
+#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
+#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
+#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
+
+#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
+#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
+#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
+#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
+#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511
+#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
+#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
+#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
+#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
+#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
+#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
+#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
+
+#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
+#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
+#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
+#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
+#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
+#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
+
+#define CONFIG_HPS_CLK_OSC1_HZ 25000000
+#define CONFIG_HPS_CLK_OSC2_HZ 25000000
+#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
+#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
+#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000
+#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
+#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
+#define CONFIG_HPS_CLK_EMAC0_HZ 1953125
+#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
+#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
+#define CONFIG_HPS_CLK_NAND_HZ 50000000
+#define CONFIG_HPS_CLK_SDMMC_HZ 200000000
+#define CONFIG_HPS_CLK_QSPI_HZ 400000000
+#define CONFIG_HPS_CLK_SPIM_HZ 12500000
+#define CONFIG_HPS_CLK_CAN0_HZ 12500000
+#define CONFIG_HPS_CLK_CAN1_HZ 12500000
+#define CONFIG_HPS_CLK_GPIODB_HZ 32000
+#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
+#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
+
+#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
+#define CONFIG_HPS_ALTERAGRP_MAINCLK 3
+#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3
+
+
+#endif /* __SOCFPGA_PLL_CONFIG_H__ */
diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h
new file mode 100644
index 0000000..edbaf89
--- /dev/null
+++ b/board/sr1500/qts/sdram_config.h
@@ -0,0 +1,341 @@ 
+/*
+ * Altera SoCFPGA SDRAM configuration
+ *
+ * SPDX-License-Identifier:	BSD-3-Clause
+ */
+
+#ifndef __SOCFPGA_SDRAM_CONFIG_H__
+#define __SOCFPGA_SDRAM_CONFIG_H__
+
+/* SDRAM configuration */
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR		0x5A56A
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP		0xB00088
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH		0x44555
+#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP		0x2C011000
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN		0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL			8
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE			2
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS			0
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN		1
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT		10
+#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH		2
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS		10
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS		15
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH		8
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH		32
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE			1
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL			0
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL			6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW			16
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC			140
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD			5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI		1560
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR		6
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR		4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD			4
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS			14
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC			20
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP			5
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT		3
+#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT		512
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC			0
+#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE			0
+#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST			0x330
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK		3
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES	0
+#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES	8
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0	0x20820820
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32	0x8208208
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0	0
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4	0x41041041
+#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36	0x410410
+#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY		0x3FFD1088
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32	0x01010101
+#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64	0x0101
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0	0x21084210
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32	0x1EF84
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0	0x2020
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14	0x0
+#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46	0xF800
+#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0		0x200
+#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN		0
+#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP		0x760210
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL			2
+#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA		0
+#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP		0x980543
+
+/* Sequencer auto configuration */
+#define RW_MGR_ACTIVATE_0_AND_1	0x0D
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT1	0x0E
+#define RW_MGR_ACTIVATE_0_AND_1_WAIT2	0x10
+#define RW_MGR_ACTIVATE_1	0x0F
+#define RW_MGR_CLEAR_DQS_ENABLE	0x49
+#define RW_MGR_GUARANTEED_READ	0x4C
+#define RW_MGR_GUARANTEED_READ_CONT	0x54
+#define RW_MGR_GUARANTEED_WRITE	0x18
+#define RW_MGR_GUARANTEED_WRITE_WAIT0	0x1B
+#define RW_MGR_GUARANTEED_WRITE_WAIT1	0x1F
+#define RW_MGR_GUARANTEED_WRITE_WAIT2	0x19
+#define RW_MGR_GUARANTEED_WRITE_WAIT3	0x1D
+#define RW_MGR_IDLE	0x00
+#define RW_MGR_IDLE_LOOP1	0x7B
+#define RW_MGR_IDLE_LOOP2	0x7A
+#define RW_MGR_INIT_RESET_0_CKE_0	0x6F
+#define RW_MGR_INIT_RESET_1_CKE_0	0x74
+#define RW_MGR_LFSR_WR_RD_BANK_0	0x22
+#define RW_MGR_LFSR_WR_RD_BANK_0_DATA	0x25
+#define RW_MGR_LFSR_WR_RD_BANK_0_DQS	0x24
+#define RW_MGR_LFSR_WR_RD_BANK_0_NOP	0x23
+#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT	0x32
+#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1	0x21
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0	0x36
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA	0x39
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS	0x38
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP	0x37
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT	0x46
+#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1	0x35
+#define RW_MGR_MRS0_DLL_RESET	0x02
+#define RW_MGR_MRS0_DLL_RESET_MIRR	0x08
+#define RW_MGR_MRS0_USER	0x07
+#define RW_MGR_MRS0_USER_MIRR	0x0C
+#define RW_MGR_MRS1	0x03
+#define RW_MGR_MRS1_MIRR	0x09
+#define RW_MGR_MRS2	0x04
+#define RW_MGR_MRS2_MIRR	0x0A
+#define RW_MGR_MRS3	0x05
+#define RW_MGR_MRS3_MIRR	0x0B
+#define RW_MGR_PRECHARGE_ALL	0x12
+#define RW_MGR_READ_B2B	0x59
+#define RW_MGR_READ_B2B_WAIT1	0x61
+#define RW_MGR_READ_B2B_WAIT2	0x6B
+#define RW_MGR_REFRESH_ALL	0x14
+#define RW_MGR_RETURN	0x01
+#define RW_MGR_SGLE_READ	0x7D
+#define RW_MGR_ZQCL	0x06
+
+/* Sequencer defines configuration */
+#define AFI_RATE_RATIO	1
+#define CALIB_LFIFO_OFFSET	7
+#define CALIB_VFIFO_OFFSET	5
+#define ENABLE_SUPER_QUICK_CALIBRATION	0
+#define IO_DELAY_PER_DCHAIN_TAP	25
+#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP	25
+#define IO_DELAY_PER_OPA_TAP	312
+#define IO_DLL_CHAIN_LENGTH	8
+#define IO_DQDQS_OUT_PHASE_MAX	0
+#define IO_DQS_EN_DELAY_MAX	31
+#define IO_DQS_EN_DELAY_OFFSET	0
+#define IO_DQS_EN_PHASE_MAX	7
+#define IO_DQS_IN_DELAY_MAX	31
+#define IO_DQS_IN_RESERVE	4
+#define IO_DQS_OUT_RESERVE	4
+#define IO_IO_IN_DELAY_MAX	31
+#define IO_IO_OUT1_DELAY_MAX	31
+#define IO_IO_OUT2_DELAY_MAX	0
+#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS	0
+#define MAX_LATENCY_COUNT_WIDTH	5
+#define READ_VALID_FIFO_SIZE	16
+#define REG_FILE_INIT_SEQ_SIGNATURE	0x55550496
+#define RW_MGR_MEM_ADDRESS_MIRRORING	0
+#define RW_MGR_MEM_DATA_MASK_WIDTH	4
+#define RW_MGR_MEM_DATA_WIDTH	32
+#define RW_MGR_MEM_DQ_PER_READ_DQS	8
+#define RW_MGR_MEM_DQ_PER_WRITE_DQS	8
+#define RW_MGR_MEM_IF_READ_DQS_WIDTH	4
+#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH	4
+#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM	1
+#define RW_MGR_MEM_NUMBER_OF_RANKS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS	1
+#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS	1
+#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH	4
+#define TINIT_CNTR0_VAL	99
+#define TINIT_CNTR1_VAL	32
+#define TINIT_CNTR2_VAL	32
+#define TRESET_CNTR0_VAL	99
+#define TRESET_CNTR1_VAL	99
+#define TRESET_CNTR2_VAL	10
+
+/* Sequencer ac_rom_init configuration */
+const u32 ac_rom_init[] = {
+	0x20700000,
+	0x20780000,
+	0x10080421,
+	0x10080520,
+	0x10090044,
+	0x100a0008,
+	0x100b0000,
+	0x10380400,
+	0x10080441,
+	0x100804c0,
+	0x100a0024,
+	0x10090010,
+	0x100b0000,
+	0x30780000,
+	0x38780000,
+	0x30780000,
+	0x10680000,
+	0x106b0000,
+	0x10280400,
+	0x10480000,
+	0x1c980000,
+	0x1c9b0000,
+	0x1c980008,
+	0x1c9b0008,
+	0x38f80000,
+	0x3cf80000,
+	0x38780000,
+	0x18180000,
+	0x18980000,
+	0x13580000,
+	0x135b0000,
+	0x13580008,
+	0x135b0008,
+	0x33780000,
+	0x10580008,
+	0x10780000
+};
+
+/* Sequencer inst_rom_init configuration */
+const u32 inst_rom_init[] = {
+	0x80000,
+	0x80680,
+	0x8180,
+	0x8200,
+	0x8280,
+	0x8300,
+	0x8380,
+	0x8100,
+	0x8480,
+	0x8500,
+	0x8580,
+	0x8600,
+	0x8400,
+	0x800,
+	0x8680,
+	0x880,
+	0xa680,
+	0x80680,
+	0x900,
+	0x80680,
+	0x980,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xb68,
+	0xcce8,
+	0xae8,
+	0x8ce8,
+	0xb88,
+	0xec88,
+	0xa08,
+	0xac88,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0x20ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x60e80,
+	0x61080,
+	0x61080,
+	0x61080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0xce00,
+	0xcd80,
+	0xe700,
+	0xc00,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0x30ce0,
+	0xd00,
+	0x680,
+	0x680,
+	0x680,
+	0x680,
+	0x70e80,
+	0x71080,
+	0x71080,
+	0x71080,
+	0xa680,
+	0x8680,
+	0x80680,
+	0x1158,
+	0x6d8,
+	0x80680,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0x87e8,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x1168,
+	0x7e8,
+	0x7e8,
+	0xa7e8,
+	0x80680,
+	0x40e88,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x40f68,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0xa680,
+	0x40fe8,
+	0x410e8,
+	0x410e8,
+	0x410e8,
+	0x41008,
+	0x41088,
+	0x41088,
+	0x41088,
+	0x1100,
+	0xc680,
+	0x8680,
+	0xe680,
+	0x80680,
+	0x0,
+	0x8000,
+	0xa000,
+	0xc000,
+	0x80000,
+	0x80,
+	0x8080,
+	0xa080,
+	0xc080,
+	0x80080,
+	0x9180,
+	0x8680,
+	0xa680,
+	0x80680,
+	0x40f08,
+	0x80680
+};
+
+#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
diff --git a/board/sr1500/socfpga.c b/board/sr1500/socfpga.c
new file mode 100644
index 0000000..35d68a9
--- /dev/null
+++ b/board/sr1500/socfpga.c
@@ -0,0 +1,151 @@ 
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/gpio.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* Address of boot parameters for ATAG (if ATAG is used) */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	int ret;
+
+	/* Reset the Marvell PHY 88E1510 */
+	ret = gpio_request(63, "PHY reset");
+	if (ret)
+		return ret;
+
+	gpio_direction_output(63, 0);
+	mdelay(10);
+	gpio_set_value(63, 1);
+	mdelay(10);
+
+	return 0;
+}
+
+#define CONFIG_SYS_IDT_CLK_ADDR		0x6a
+
+static int do_clksave(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	u8 buf[1];
+
+	buf[0] = 0x01;
+	i2c_write(CONFIG_SYS_IDT_CLK_ADDR, 0, 0, buf, 1);
+
+	return 0;
+}
+
+U_BOOT_CMD(clksave, 1, 0, do_clksave,
+	   "IDT 5V49EE702 Progsave command", "");
+
+#define NET_DEV_NAME			"ethernet@ff702000"
+#define MII_MARVELL_PHY_PAGE		22
+#define PHY_DIAG_START			(1 << 15)
+#define PHY_DIAG_BUSY			(1 << 11)
+#define PHY_DIAG_TIMEOUT		5000	/* 5 seconds */
+
+static char *pair_state(int val, char *str)
+{
+	switch (val) {
+	case 0x00:
+		strcpy(str, "Invalid");
+		break;
+	case 0x01:
+		strcpy(str, "Pair Ok");
+		break;
+	case 0x02:
+		strcpy(str, "Pair Open");
+		break;
+	case 0x03:
+		strcpy(str, "Same Pair Short");
+		break;
+	case 0x04:
+		strcpy(str, "Cross Pair Short");
+		break;
+	case 0x09:
+		strcpy(str, "Pair Busy");
+		break;
+	default:
+		strcpy(str, "Reserved");
+		break;
+	};
+
+	return str;
+}
+
+static int do_phytest(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+	const char devname[] = NET_DEV_NAME;
+	unsigned long ts;
+	char str[32];
+	u8 addr = 0;
+	u16 data;
+	u16 status;
+	u16 oldpage;
+	int i;
+
+	/* Save current page register */
+	miiphy_read(devname, addr, MII_MARVELL_PHY_PAGE, &oldpage);
+
+	/*
+	 * Run cable disgnostics
+	 */
+	printf("Running cable diagnostic test...");
+	miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, 7);
+	miiphy_write(devname, addr, 21, PHY_DIAG_START);
+
+	ts = get_timer(0);
+	do {
+		miiphy_read(devname, addr, 21, &data);
+		if ((data & PHY_DIAG_BUSY) != PHY_DIAG_BUSY)
+			break;
+
+		mdelay(1);
+	} while (get_timer(ts) < PHY_DIAG_TIMEOUT);
+	printf("done!\n");
+
+	miiphy_read(devname, addr, 20, &status);
+
+	for (i = 0; i < 4; i++) {
+		int val;
+
+		val = (status >> (i * 4)) & 0x000f;
+		pair_state(val, str);
+		printf("Pair %d: %s", i, str);
+
+		/* Only print fault length if not okay */
+		if (val != 0x01) {
+			miiphy_read(devname, addr, 16 + i, &data);
+			printf(" - Length to fault %d cm", data);
+		}
+		printf("\n");
+	}
+
+	/* Restore original page */
+	miiphy_write(devname, addr, MII_MARVELL_PHY_PAGE, oldpage);
+
+	return 0;
+}
+
+U_BOOT_CMD(phytest, 1, 1, do_phytest,
+	   "Marvell PHY test command - dump some values", "");
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
new file mode 100644
index 0000000..11dea35
--- /dev/null
+++ b/configs/socfpga_sr1500_defconfig
@@ -0,0 +1,17 @@ 
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_SPL_DM=y
+CONFIG_DM_GPIO=y
+CONFIG_TARGET_SOCFPGA_SR1500=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_sr1500"
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_SPL_STACK_R_ADDR=0x00800000
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
diff --git a/doc/README.socfpga b/doc/README.socfpga
index cfcbbfe..eebf373 100644
--- a/doc/README.socfpga
+++ b/doc/README.socfpga
@@ -7,7 +7,6 @@  This README is about U-Boot and SPL support for Altera's ARM Cortex-A9MPCore
 based SOCFPGA. To know more about the hardware itself, please refer to
 www.altera.com.
 
-
 --------------------------------------------
 socfpga_dw_mmc
 --------------------------------------------
@@ -51,3 +50,76 @@  the card
 #define CONFIG_SOCFPGA_DWMMC_BUS_HZ	50000000
 -> The clock rate to controller. Do note the controller have a wrapper which
 divide the clock from PLL by 4.
+
+-------------------------------------------------------------------------
+Generating the header files for SPL intergration as a replacement for the
+Preloader
+-------------------------------------------------------------------------
+This text assumes the use of Quartus 14.0.200
+
+I) Rebuilding the MCVEVK Quartus project
+----------------------------------------
+ 1) Navigate to DENX_MCV_reference_* directory
+ 2) Run Quartus II
+ 3) Open Project (Ctrl+J), select DENX_MCV_reference.qpf
+ 4) Run QSys [Tools->QSys]
+    4.1) In the Open dialog, select 'mcv_hps.qsys'
+    4.2) In the Open System dialog, wait until completion and press 'Close'
+    4.3) In the Qsys window, click on 'Generate HDL...' in bottom right corner
+         4.3.1) In the 'Generation' window, click 'Generate'
+	 4.3.2) In the 'Generate' dialog, wait until completion and click 'Close'
+    4.4) In the QSys window, click 'Finish'
+         4.4.1) In the 'Quartus II' pop up window, click 'OK'
+ 5) Back in Quartus II main window, do the following
+    5.1) Use Processing -> Start -> Start Analysis & Synthesis (Ctrl+K)
+    5.2) Use Processing -> Start Compilation (Ctrl+L)
+    ... have lunch, coffee, play games ...
+
+ [
+   NOTE: Steps 2-5 above can be also done using a convenience scripts
+         from the command line:
+	 $ ./qsys.sh && ./anal.sh && ./build.sh
+ ]
+
+ 6) Launch a separate terminal window
+    6.1) Change directory to 'software/spl_bsp'
+    6.2) Export path to embedded command shell and friends
+         $ export PATH=/work/DENX/Altera/Quartus/14.0/embedded/:$PATH
+    6.3) Start embedded command shell (ECS)
+         $ embedded_command_shell.sh
+    6.4) Prepare BSP by launching the BSP editor from ECS
+         => bsp-editor
+    6.5) In BSP editor
+         6.5.1) Use File -> Open
+	 6.5.2) Select 'settings.bsp' file
+	 6.5.4) Click Generate
+	 6.5.5) Click Exit
+
+Now the necessary files are generated. And U-Boot can be used
+to generate the SPL header files. For this, please use the
+following script:
+
+./arch/arm/mach-socfpga/qts-filter.sh cyclone5 \
+	/path/to/quartus/project /path/to/output/qts/
+
+This will generate the following 4 files:
+
+iocsr_config.h
+pinmux_config.h
+pll_config.h
+sdram_config.h
+
+These files need to be copied into "qts" directory in the board
+directory. Here the example for the DENX MCVEVK:
+
+$ ll board/denx/mcvevk/qts/
+total 44
+drwxrwxr-x 2 stefan stefan 4096 Okt 20 07:07 ./
+drwxrwxr-x 3 stefan stefan 4096 Okt 21 13:06 ../
+-rw-rw-r-- 1 stefan stefan 8826 Okt 20 07:07 iocsr_config.h
+-rw-rw-r-- 1 stefan stefan 4398 Okt 20 07:07 pinmux_config.h
+-rw-rw-r-- 1 stefan stefan 3192 Okt 20 07:07 pll_config.h
+-rw-rw-r-- 1 stefan stefan 9031 Okt 20 07:07 sdram_config.h
+
+Now you board is ready for full mainline support including
+U-Boot SPL. The Preloader will not be needed any more.
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
new file mode 100644
index 0000000..def01fb
--- /dev/null
+++ b/include/configs/socfpga_sr1500.h
@@ -0,0 +1,113 @@ 
+/*
+ * Copyright (C) 2015 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+#ifndef __CONFIG_SOCFPGA_SR1500_H__
+#define __CONFIG_SOCFPGA_SR1500_H__
+
+#include <asm/arch/socfpga_base_addrs.h>
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_DOS_PARTITION
+#define CONFIG_FAT_WRITE
+
+#define CONFIG_HW_WATCHDOG
+
+/* U-Boot Commands */
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TIME
+
+/* Memory configurations */
+#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SR1500 */
+
+/* Booting Linux */
+#define CONFIG_BOOTDELAY	3
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_BOOTARGS		"console=ttyS0" __stringify(CONFIG_BAUDRATE)
+#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
+#define CONFIG_LOADADDR		0x8000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define CONFIG_SYS_CONSOLE_INFO_QUIET	/* don't print console @ startup */
+
+/* Ethernet on SoC (EMAC) */
+#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII
+/* The PHY is autodetected, so no MII PHY address is needed here */
+#define CONFIG_PHY_MARVELL
+#define PHY_ANEG_TIMEOUT	8000
+
+/* Extra Environment */
+#define CONFIG_HOSTNAME		sr1500
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"verify=n\0" \
+	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
+		"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"bootimage=zImage\0" \
+	"fdt_addr=100\0" \
+	"fdtimage=socfpga.dtb\0" \
+		"fsloadcmd=ext2load\0" \
+	"bootm ${loadaddr} - ${fdt_addr}\0" \
+	"mmcroot=/dev/mmcblk0p2\0" \
+	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${mmcroot} rw rootwait;" \
+		"bootz ${loadaddr} - ${fdt_addr}\0" \
+	"mmcload=mmc rescan;" \
+		"load mmc 0:1 ${loadaddr} ${bootimage};" \
+		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+	"qspiroot=/dev/mtdblock0\0" \
+	"qspirootfstype=jffs2\0" \
+	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
+		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
+		"bootm ${loadaddr} - ${fdt_addr}\0"
+
+/* Environment */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+
+/* Enable SPI NOR flash reset, needed for SPI booting */
+#define CONFIG_SPI_N25Q256A_RESET
+
+/* Environment setting for SPI flash */
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
+#define CONFIG_ENV_SIZE		(16 * 1024)
+#define CONFIG_ENV_OFFSET	0x00040000
+#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SPI_BUS	0
+#define CONFIG_ENV_SPI_CS	0
+#define CONFIG_ENV_SPI_MODE	SPI_MODE_3
+#define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
+
+/* U-Boot payload is stored at offset 0x60000 */
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x60000
+
+/*
+ * Bootcounter
+ */
+#define CONFIG_BOOTCOUNT_LIMIT
+/* last 2 lwords in OCRAM */
+#define CONFIG_SYS_BOOTCOUNT_ADDR	0xfffffff8
+#define CONFIG_SYS_BOOTCOUNT_BE
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFPGA_SR1500_H__ */