From patchwork Tue May 25 12:09:03 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Igor V. Kovalenko" X-Patchwork-Id: 53540 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B2069B7D42 for ; Tue, 25 May 2010 22:11:18 +1000 (EST) Received: from localhost ([127.0.0.1]:33745 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OGsy6-0002Z8-5Q for incoming@patchwork.ozlabs.org; Tue, 25 May 2010 08:10:46 -0400 Received: from [140.186.70.92] (port=47761 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OGswX-0002Ip-Lv for qemu-devel@nongnu.org; Tue, 25 May 2010 08:09:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OGswT-00007p-6k for qemu-devel@nongnu.org; Tue, 25 May 2010 08:09:09 -0400 Received: from mail-fx0-f45.google.com ([209.85.161.45]:45783) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OGswT-00005W-26 for qemu-devel@nongnu.org; Tue, 25 May 2010 08:09:05 -0400 Received: by mail-fx0-f45.google.com with SMTP id 10so306042fxm.4 for ; Tue, 25 May 2010 05:09:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:subject:to:from:date :message-id:in-reply-to:references:user-agent:mime-version :content-type:content-transfer-encoding; bh=j0XzBc6HGsFcvB3Czhqqxg6XgfQI5xDP26MIfENr55o=; b=Le6kDeNDpIvoHN7d7Fna5WxrCL/npcJovjWbX7fViKDKH01LLa/p2irJb2qvvOOpye CUptP/Sn6DHP7tW/FhyOIczP+S6DGPZaL0Slse0lso4n8tfU5Kw9TYCrmxfkjPPnU7bW STEVF0KrcqfcH4eFiLhiyubwdgN8sPuceyC7I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:to:from:date:message-id:in-reply-to:references:user-agent :mime-version:content-type:content-transfer-encoding; b=iyF8xKFqFFwA1Bm57jhBtlKtlCx13IzNhlTIE+aMpV67mEiO9k5g2DDOE4VmGmyezH FXaz2rwSCnqejXl4iu80U8cApj4FqdLxaS27e2RVY1ixZ757GpT+ViGy+Vo+P8JU0fRt 6t+ziFStlyqCGje3eDU6gDdR1FEsplTBZZmt4= Received: by 10.223.17.136 with SMTP id s8mr6129373faa.41.1274789344790; Tue, 25 May 2010 05:09:04 -0700 (PDT) Received: from skyserv ([87.255.14.75]) by mx.google.com with ESMTPS id 13sm24521770fad.19.2010.05.25.05.09.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 25 May 2010 05:09:04 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=[192.168.1.2]) by skyserv with esmtp (Exim 4.71) (envelope-from ) id 1OGswR-0004yh-6Z for qemu-devel@nongnu.org; Tue, 25 May 2010 16:09:03 +0400 To: qemu-devel@nongnu.org From: "Igor V. Kovalenko" Date: Tue, 25 May 2010 16:09:03 +0400 Message-ID: <20100525120903.19024.14235.stgit@skyserv> In-Reply-To: <20100525120646.19024.70552.stgit@skyserv> References: <20100525120646.19024.70552.stgit@skyserv> User-Agent: StGit/0.15 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Subject: [Qemu-devel] [PATCH 2/2] sparc64: clean up pci bridge map X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Igor V. Kovalenko - remove unused host state and store pci bus pointer only - do not map host state access into unused 1fe.10000000 range - reorder pci region registration - assign pci i/o region to isa_mem_base Signed-off-by: Igor V. Kovalenko --- hw/apb_pci.c | 49 ++++++++++++++++++++++++++----------------------- hw/sun4u.c | 4 ++-- 2 files changed, 28 insertions(+), 25 deletions(-) diff --git a/hw/apb_pci.c b/hw/apb_pci.c index 65d8ba6..b53e3c3 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -65,7 +65,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) typedef struct APBState { SysBusDevice busdev; - PCIHostState host_state; + PCIBus *bus; ReadWriteHandler pci_config_handler; uint32_t iommu[4]; uint32_t pci_control[16]; @@ -191,7 +191,7 @@ static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr, val = qemu_bswap_len(val, size); APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val); - pci_data_write(s->host_state.bus, addr, val, size); + pci_data_write(s->bus, addr, val, size); } static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr, @@ -200,7 +200,7 @@ static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr, uint32_t ret; APBState *s = container_of(h, APBState, pci_config_handler); - ret = pci_data_read(s->host_state.bus, addr, size); + ret = pci_data_read(s->bus, addr, size); ret = qemu_bswap_len(ret, size); APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret); return ret; @@ -331,37 +331,37 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base, s = sysbus_from_qdev(dev); /* apb_config */ sysbus_mmio_map(s, 0, special_base); + /* PCI configuration space */ + sysbus_mmio_map(s, 1, special_base + 0x1000000ULL); /* pci_ioport */ - sysbus_mmio_map(s, 1, special_base + 0x2000000ULL); - /* pci_config */ - sysbus_mmio_map(s, 2, special_base + 0x1000000ULL); - /* mem_data */ - sysbus_mmio_map(s, 3, mem_base); + sysbus_mmio_map(s, 2, special_base + 0x2000000ULL); d = FROM_SYSBUS(APBState, s); - d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", + + d->bus = pci_register_bus(&d->busdev.qdev, "pci", pci_apb_set_irq, pci_pbm_map_irq, d, 0, 32); - pci_bus_set_mem_base(d->host_state.bus, mem_base); + pci_bus_set_mem_base(d->bus, mem_base); for (i = 0; i < 32; i++) { sysbus_connect_irq(s, i, pic[i]); } - pci_create_simple(d->host_state.bus, 0, "pbm"); + pci_create_simple(d->bus, 0, "pbm"); + /* APB secondary busses */ - *bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0), + *bus2 = pci_bridge_init(d->bus, PCI_DEVFN(1, 0), PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq, "Advanced PCI Bus secondary bridge 1"); apb_pci_bridge_init(*bus2); - *bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1), + *bus3 = pci_bridge_init(d->bus, PCI_DEVFN(1, 1), PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq, "Advanced PCI Bus secondary bridge 2"); apb_pci_bridge_init(*bus3); - return d->host_state.bus; + return d->bus; } static void pci_pbm_reset(DeviceState *d) @@ -382,7 +382,7 @@ static void pci_pbm_reset(DeviceState *d) static int pci_pbm_init_device(SysBusDevice *dev) { APBState *s; - int pci_mem_data, apb_config, pci_ioport, pci_config; + int pci_config, apb_config, pci_ioport; unsigned int i; s = FROM_SYSBUS(APBState, dev); @@ -396,20 +396,23 @@ static int pci_pbm_init_device(SysBusDevice *dev) /* apb_config */ apb_config = cpu_register_io_memory(apb_config_read, apb_config_write, s); + /* at region 0 */ sysbus_init_mmio(dev, 0x10000ULL, apb_config); - /* pci_ioport */ - pci_ioport = cpu_register_io_memory(pci_apb_ioread, - pci_apb_iowrite, s); - sysbus_init_mmio(dev, 0x10000ULL, pci_ioport); - /* pci_config */ + + /* PCI configuration space */ s->pci_config_handler.read = apb_pci_config_read; s->pci_config_handler.write = apb_pci_config_write; pci_config = cpu_register_io_memory_simple(&s->pci_config_handler); assert(pci_config >= 0); + /* at region 1 */ sysbus_init_mmio(dev, 0x1000000ULL, pci_config); - /* mem_data */ - pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1); - sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data); + + /* pci_ioport */ + pci_ioport = cpu_register_io_memory(pci_apb_ioread, + pci_apb_iowrite, s); + /* at region 2 */ + sysbus_init_mmio(dev, 0x10000ULL, pci_ioport); + return 0; } diff --git a/hw/sun4u.c b/hw/sun4u.c index 1e92900..40b5f1f 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -70,7 +70,7 @@ #define PROM_VADDR 0x000ffd00000ULL #define APB_SPECIAL_BASE 0x1fe00000000ULL #define APB_MEM_BASE 0x1ff00000000ULL -#define VGA_BASE (APB_MEM_BASE + 0x400000ULL) +#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) #define PROM_FILENAME "openbios-sparc64" #define NVRAM_SIZE 0x2000 #define MAX_IDE_BUS 2 @@ -766,7 +766,7 @@ static void sun4uv_init(ram_addr_t RAM_size, irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2, &pci_bus3); - isa_mem_base = VGA_BASE; + isa_mem_base = APB_PCI_IO_BASE; pci_vga_init(pci_bus, 0, 0); // XXX Should be pci_bus3