From patchwork Mon May 24 16:19:35 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nathan Froyd X-Patchwork-Id: 53437 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C3D5DB7D1E for ; Tue, 25 May 2010 02:22:28 +1000 (EST) Received: from localhost ([127.0.0.1]:58040 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OGaPa-00025B-R3 for incoming@patchwork.ozlabs.org; Mon, 24 May 2010 12:21:54 -0400 Received: from [140.186.70.92] (port=49896 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OGaNc-0001uD-Ol for qemu-devel@nongnu.org; Mon, 24 May 2010 12:20:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OGaNW-000140-Qa for qemu-devel@nongnu.org; Mon, 24 May 2010 12:19:49 -0400 Received: from mail.codesourcery.com ([38.113.113.100]:33392) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OGaNV-00012w-Vv for qemu-devel@nongnu.org; Mon, 24 May 2010 12:19:46 -0400 Received: (qmail 27882 invoked from network); 24 May 2010 16:19:44 -0000 Received: from unknown (HELO localhost) (froydnj@127.0.0.2) by mail.codesourcery.com with ESMTPA; 24 May 2010 16:19:44 -0000 From: Nathan Froyd To: qemu-devel@nongnu.org Date: Mon, 24 May 2010 09:19:35 -0700 Message-Id: <1274717984-25887-2-git-send-email-froydnj@codesourcery.com> X-Mailer: git-send-email 1.6.3.2 In-Reply-To: <1274717984-25887-1-git-send-email-froydnj@codesourcery.com> References: <1274717984-25887-1-git-send-email-froydnj@codesourcery.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH 01/10] target-mips: break out [ls][wd]c1 and rdhwr insn generation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Nathan Froyd Acked-by: Richard Henderson --- target-mips/translate.c | 106 ++++++++++++++++++++++++++--------------------- 1 files changed, 59 insertions(+), 47 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index c95ecb1..2075d09 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1220,6 +1220,17 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, tcg_temp_free(t0); } +static void gen_cop1_ldst(CPUState *env, DisasContext *ctx, + uint32_t op, int rt, int rs, int16_t imm) +{ + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + gen_flt_ldst(ctx, op, rt, rs, imm); + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } +} + /* Arithmetic with immediate operand */ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rs, int16_t imm) @@ -7528,6 +7539,52 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, fregnames[fs], fregnames[ft]); } +static void +gen_rdhwr (CPUState *env, DisasContext *ctx, int rt, int rd) +{ + TCGv t0; + + check_insn(env, ctx, ISA_MIPS32R2); + t0 = tcg_temp_new(); + + switch (rd) { + case 0: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_cpunum(t0); + gen_store_gpr(t0, rt); + break; + case 1: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_synci_step(t0); + gen_store_gpr(t0, rt); + break; + case 2: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_cc(t0); + gen_store_gpr(t0, rt); + break; + case 3: + save_cpu_state(ctx, 1); + gen_helper_rdhwr_ccres(t0); + gen_store_gpr(t0, rt); + break; + case 29: +#if defined(CONFIG_USER_ONLY) + tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value)); + gen_store_gpr(t0, rt); + break; +#else + /* XXX: Some CPUs implement this in hardware. + Not supported yet. */ +#endif + default: /* Invalid */ + MIPS_INVAL("rdhwr"); + generate_exception(ctx, EXCP_RI); + break; + } + tcg_temp_free(t0); +} + static void handle_delay_slot (CPUState *env, DisasContext *ctx, int insn_bytes) { @@ -8999,47 +9056,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch) gen_bshfl(ctx, op2, rt, rd); break; case OPC_RDHWR: - check_insn(env, ctx, ISA_MIPS32R2); - { - TCGv t0 = tcg_temp_new(); - - switch (rd) { - case 0: - save_cpu_state(ctx, 1); - gen_helper_rdhwr_cpunum(t0); - gen_store_gpr(t0, rt); - break; - case 1: - save_cpu_state(ctx, 1); - gen_helper_rdhwr_synci_step(t0); - gen_store_gpr(t0, rt); - break; - case 2: - save_cpu_state(ctx, 1); - gen_helper_rdhwr_cc(t0); - gen_store_gpr(t0, rt); - break; - case 3: - save_cpu_state(ctx, 1); - gen_helper_rdhwr_ccres(t0); - gen_store_gpr(t0, rt); - break; - case 29: -#if defined(CONFIG_USER_ONLY) - tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value)); - gen_store_gpr(t0, rt); - break; -#else - /* XXX: Some CPUs implement this in hardware. - Not supported yet. */ -#endif - default: /* Invalid */ - MIPS_INVAL("rdhwr"); - generate_exception(ctx, EXCP_RI); - break; - } - tcg_temp_free(t0); - } + gen_rdhwr(env, ctx, rt, rd); break; case OPC_FORK: check_insn(env, ctx, ASE_MT); @@ -9242,12 +9259,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch) case OPC_LDC1: case OPC_SWC1: case OPC_SDC1: - if (env->CP0_Config1 & (1 << CP0C1_FP)) { - check_cp1_enabled(ctx); - gen_flt_ldst(ctx, op, rt, rs, imm); - } else { - generate_exception_err(ctx, EXCP_CpU, 1); - } + gen_cop1_ldst(env, ctx, op, rt, rs, imm); break; case OPC_CP1: