Patchwork [5/5] sparc64: flush translations on mmu context change

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Submitter Igor V. Kovalenko
Date May 22, 2010, 10:52 a.m.
Message ID <20100522105240.18257.19008.stgit@skyserv>
Download mbox | patch
Permalink /patch/53270/
State New
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Comments

Igor V. Kovalenko - May 22, 2010, 10:52 a.m.
From: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>

- two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers
  using value of DMMU primary and secondary context registers, so we need to
  flush softmmu translations when context registers are changed

Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
---
 target-sparc/op_helper.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

Patch

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index 28224b2..edeeb44 100644
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -2959,9 +2959,15 @@  void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size)
                 break;
             case 1: // Primary context
                 env->dmmu.mmu_primary_context = val;
+                /* can be optimized to only flush MMU_USER_IDX
+                   and MMU_KERNEL_IDX entries */
+                tlb_flush(env, 1);
                 break;
             case 2: // Secondary context
                 env->dmmu.mmu_secondary_context = val;
+                /* can be optimized to only flush MMU_USER_SECONDARY_IDX
+                   and MMU_KERNEL_SECONDARY_IDX entries */
+                tlb_flush(env, 1);
                 break;
             case 5: // TSB access
                 DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"