From patchwork Fri Oct 9 08:17:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jisheng Zhang X-Patchwork-Id: 528131 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 2BBD51406AA for ; Fri, 9 Oct 2015 19:23:36 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933728AbbJIIXQ (ORCPT ); Fri, 9 Oct 2015 04:23:16 -0400 Received: from mx0b-0016f401.pphosted.com ([67.231.156.173]:11249 "EHLO mx0b-0016f401.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933559AbbJIIVh (ORCPT ); Fri, 9 Oct 2015 04:21:37 -0400 Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.15.0.59/8.15.0.59) with SMTP id t998KEMk026335; Fri, 9 Oct 2015 01:21:02 -0700 Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 1xaehjnn20-1 (version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 09 Oct 2015 01:21:02 -0700 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Fri, 9 Oct 2015 01:21:01 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1044.25 via Frontend Transport; Fri, 9 Oct 2015 01:21:00 -0700 Received: from xhacker.marvell.com (unknown [10.37.135.134]) by maili.marvell.com (Postfix) with ESMTP id D2B273F7045; Fri, 9 Oct 2015 01:20:58 -0700 (PDT) From: Jisheng Zhang To: , , CC: , , , , , , , , , , , Jisheng Zhang Subject: [PATCH v4 6/6] arm64: dts: berlin4ct: add default pinmux for uart0 Date: Fri, 9 Oct 2015 16:17:09 +0800 Message-ID: <1444378629-3057-7-git-send-email-jszhang@marvell.com> X-Mailer: git-send-email 2.6.1 In-Reply-To: <1444378629-3057-1-git-send-email-jszhang@marvell.com> References: <1444378629-3057-1-git-send-email-jszhang@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2015-10-09_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=inbound_notspam policy=inbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1507310000 definitions=main-1510090108 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add urt0 txd and rxd muxing setup in the dtsi because uart0 always uses them to work, no other possibilities. Signed-off-by: Jisheng Zhang Acked-by: Antoine Tenart --- arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi index 8e66355..a4a1876 100644 --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi @@ -288,12 +288,19 @@ clocks = <&osc>; reg-shift = <2>; status = "disabled"; + pinctrl-0 = <&uart0_pmux>; + pinctrl-names = "default"; }; }; system_pinctrl: pin-controller@fe2200 { compatible = "marvell,berlin4ct-system-pinctrl"; reg = <0xfe2200 0xc>; + + uart0_pmux: uart0-pmux { + groups = "SM_URT0_TXD", "SM_URT0_RXD"; + function = "uart0"; + }; }; }; };