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MIPS DINSU

Message ID 4BF13485.8000903@mvista.com
State New
Headers show

Commit Message

Dmitry Antipov May 17, 2010, 12:20 p.m. UTC 
Hello,

shouldn't it be in that way?

Dmitry

Comments

Aurelien Jarno May 28, 2010, 8:03 p.m. UTC | #1 
On Mon, May 17, 2010 at 04:20:21PM +0400, Dmitry Antipov wrote:
> Hello,
> 
> shouldn't it be in that way?
> 
> Dmitry
> 

Good catch, it is correct. Would you mind resending the patch with a
Signed-off-by: line?

> --- qemu-0.12.4/target-mips/translate.c	2010-05-17 16:12:58.048661610 +0400
> +++ qemu-0.12.4/target-mips/translate.c	2010-05-17 16:13:12.281656754 +0400
> @@ -2761,7 +2761,7 @@
>      case OPC_DINSU:
>          if (lsb > msb)
>              goto fail;
> -        mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb;
> +        mask = ((1ULL << (msb - lsb + 1)) - 1) << (lsb + 32);
>          gen_load_gpr(t0, rt);
>          tcg_gen_andi_tl(t0, t0, ~mask);
>          tcg_gen_shli_tl(t1, t1, lsb + 32);
diff mbox

Patch

--- qemu-0.12.4/target-mips/translate.c	2010-05-17 16:12:58.048661610 +0400
+++ qemu-0.12.4/target-mips/translate.c	2010-05-17 16:13:12.281656754 +0400
@@ -2761,7 +2761,7 @@ 
     case OPC_DINSU:
         if (lsb > msb)
             goto fail;
-        mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb;
+        mask = ((1ULL << (msb - lsb + 1)) - 1) << (lsb + 32);
         gen_load_gpr(t0, rt);
         tcg_gen_andi_tl(t0, t0, ~mask);
         tcg_gen_shli_tl(t1, t1, lsb + 32);