diff mbox

[AArch64] Update patterns to support FP zero

Message ID 003d01d101cb$83d26e50$8b774af0$@com
State New
Headers show

Commit Message

Wilco Oct. 8, 2015, 1:16 p.m. UTC 
This patch improves support for instructions that allow FP zero immediate. All FP compares generated
by various patterns should use aarch64_fp_compare_operand. LDP/STP uses aarch64_reg_or_fp_zero.
Passes regression on AArch64.

OK for commit?

ChangeLog:
2015-10-08  Wilco Dijkstra  <wdijkstr@arm.com>

	* gcc/config/aarch64/aarch64.md (cbranch<mode>4):
	Use aarch64_fp_compare_operand.
	(store_pairsf): Use aarch64_reg_or_fp_zero.
	(store_pairdf): Likewise.
	(cstore<mode>4): Use aarch64_fp_compare_operand.
	(cmov<mode>6): Likewise.
	* gcc/config/aarch64/aarch64-ldpstp.md: Use aarch64_reg_or_fp_zero.

---
 gcc/config/aarch64/aarch64-ldpstp.md | 12 ++++++------
 gcc/config/aarch64/aarch64.md        | 14 +++++++-------
 2 files changed, 13 insertions(+), 13 deletions(-)

Comments

James Greenhalgh Oct. 13, 2015, 7:56 a.m. UTC | #1 
On Thu, Oct 08, 2015 at 02:16:16PM +0100, Wilco Dijkstra wrote:
> This patch improves support for instructions that allow FP zero immediate. All FP compares generated
> by various patterns should use aarch64_fp_compare_operand. LDP/STP uses aarch64_reg_or_fp_zero.
> Passes regression on AArch64.
> 
> OK for commit?

OK.

Thanks,
James

> 
> ChangeLog:
> 2015-10-08  Wilco Dijkstra  <wdijkstr@arm.com>
> 
> 	* gcc/config/aarch64/aarch64.md (cbranch<mode>4):
> 	Use aarch64_fp_compare_operand.
> 	(store_pairsf): Use aarch64_reg_or_fp_zero.
> 	(store_pairdf): Likewise.
> 	(cstore<mode>4): Use aarch64_fp_compare_operand.
> 	(cmov<mode>6): Likewise.
> 	* gcc/config/aarch64/aarch64-ldpstp.md: Use aarch64_reg_or_fp_zero.
>
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64-ldpstp.md b/gcc/config/aarch64/aarch64-ldpstp.md
index 8d6d882..54cf34c 100644
--- a/gcc/config/aarch64/aarch64-ldpstp.md
+++ b/gcc/config/aarch64/aarch64-ldpstp.md
@@ -80,9 +80,9 @@ 
 
 (define_peephole2
   [(set (match_operand:GPF 0 "aarch64_mem_pair_operand" "")
-	(match_operand:GPF 1 "register_operand" ""))
+	(match_operand:GPF 1 "aarch64_reg_or_fp_zero" ""))
    (set (match_operand:GPF 2 "memory_operand" "")
-	(match_operand:GPF 3 "register_operand" ""))]
+	(match_operand:GPF 3 "aarch64_reg_or_fp_zero" ""))]
   "aarch64_operands_ok_for_ldpstp (operands, false, <MODE>mode)"
   [(parallel [(set (match_dup 0) (match_dup 1))
 	      (set (match_dup 2) (match_dup 3))])]
@@ -308,13 +308,13 @@ 
 (define_peephole2
   [(match_scratch:DI 8 "r")
    (set (match_operand:GPF 0 "memory_operand" "")
-	(match_operand:GPF 1 "aarch64_reg_or_zero" ""))
+	(match_operand:GPF 1 "aarch64_reg_or_fp_zero" ""))
    (set (match_operand:GPF 2 "memory_operand" "")
-	(match_operand:GPF 3 "aarch64_reg_or_zero" ""))
+	(match_operand:GPF 3 "aarch64_reg_or_fp_zero" ""))
    (set (match_operand:GPF 4 "memory_operand" "")
-	(match_operand:GPF 5 "aarch64_reg_or_zero" ""))
+	(match_operand:GPF 5 "aarch64_reg_or_fp_zero" ""))
    (set (match_operand:GPF 6 "memory_operand" "")
-	(match_operand:GPF 7 "aarch64_reg_or_zero" ""))
+	(match_operand:GPF 7 "aarch64_reg_or_fp_zero" ""))
    (match_dup 8)]
   "aarch64_operands_adjust_ok_for_ldpstp (operands, false, <MODE>mode)"
   [(const_int 0)]
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index f2d1be1..67ce01b 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -240,7 +240,7 @@ 
 (define_expand "cbranch<mode>4"
   [(set (pc) (if_then_else (match_operator 0 "aarch64_comparison_operator"
 			    [(match_operand:GPF 1 "register_operand" "")
-			     (match_operand:GPF 2 "aarch64_reg_or_zero" "")])
+			     (match_operand:GPF 2 "aarch64_fp_compare_operand" "")])
 			   (label_ref (match_operand 3 "" ""))
 			   (pc)))]
   ""
@@ -1336,9 +1336,9 @@ 
 ;; fairly lax checking on the second memory operation.
 (define_insn "store_pairsf"
   [(set (match_operand:SF 0 "aarch64_mem_pair_operand" "=Ump,Ump")
-	(match_operand:SF 1 "register_operand" "w,*r"))
+	(match_operand:SF 1 "aarch64_reg_or_fp_zero" "w,*rY"))
    (set (match_operand:SF 2 "memory_operand" "=m,m")
-	(match_operand:SF 3 "register_operand" "w,*r"))]
+	(match_operand:SF 3 "aarch64_reg_or_fp_zero" "w,*rY"))]
   "rtx_equal_p (XEXP (operands[2], 0),
 		plus_constant (Pmode,
 			       XEXP (operands[0], 0),
@@ -1352,9 +1352,9 @@ 
 
 (define_insn "store_pairdf"
   [(set (match_operand:DF 0 "aarch64_mem_pair_operand" "=Ump,Ump")
-	(match_operand:DF 1 "register_operand" "w,*r"))
+	(match_operand:DF 1 "aarch64_reg_or_fp_zero" "w,*rY"))
    (set (match_operand:DF 2 "memory_operand" "=m,m")
-	(match_operand:DF 3 "register_operand" "w,*r"))]
+	(match_operand:DF 3 "aarch64_reg_or_fp_zero" "w,*rY"))]
   "rtx_equal_p (XEXP (operands[2], 0),
 		plus_constant (Pmode,
 			       XEXP (operands[0], 0),
@@ -2901,7 +2901,7 @@ 
   [(set (match_operand:SI 0 "register_operand" "")
 	(match_operator:SI 1 "aarch64_comparison_operator"
 	 [(match_operand:GPF 2 "register_operand" "")
-	  (match_operand:GPF 3 "register_operand" "")]))]
+	  (match_operand:GPF 3 "aarch64_fp_compare_operand" "")]))]
   ""
   "
   operands[2] = aarch64_gen_compare_reg (GET_CODE (operands[1]), operands[2],
@@ -2971,7 +2971,7 @@ 
 	(if_then_else:GPF
 	 (match_operator 1 "aarch64_comparison_operator"
 	  [(match_operand:GPF 2 "register_operand" "")
-	   (match_operand:GPF 3 "register_operand" "")])
+	   (match_operand:GPF 3 "aarch64_fp_compare_operand" "")])
 	 (match_operand:GPF 4 "register_operand" "")
 	 (match_operand:GPF 5 "register_operand" "")))]
   ""