| Message ID | 560E4CAC.1080804@arm.com |
|---|---|
| State | New |
| Headers | show |
On Fri, Oct 02, 2015 at 10:21:48AM +0100, Renlin Li wrote: > Hi all, > > This is a simple patch to add csneg3_uxtw_insn into aarch64 backend. It > will save one uxtw instruction as a write to the 32-bit w-register > implicitly > zero-extends the value up to the full 64 bits of an x-register. > > aarch64-none-elf regression test Okay without any issues. Okay to commit? OK. Thanks, James > gcc/ChangeLog: > > 2015-10-02 Renlin Li <renlin.li@arm.com> > > * config/aarch64/aarch64.md (csneg3_uxtw_insn): New pattern. > > gcc/testsuite/ChangeLog: > > 2015-10-02 Renlin Li <renlin.li@arm.com> > > * gcc.target/aarch64/csneg-1.c: Update test. > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md > index c3cd58d..373f2d5 100644 > --- a/gcc/config/aarch64/aarch64.md > +++ b/gcc/config/aarch64/aarch64.md > @@ -3132,6 +3132,18 @@ > [(set_attr "type" "csel")] > ) > > +(define_insn "csneg3_uxtw_insn" > + [(set (match_operand:DI 0 "register_operand" "=r") > + (zero_extend:DI > + (if_then_else:SI > + (match_operand 1 "aarch64_comparison_operation" "") > + (neg:SI (match_operand:SI 2 "register_operand" "r")) > + (match_operand:SI 3 "aarch64_reg_or_zero" "rZ"))))] > + "" > + "csneg\\t%w0, %w3, %w2, %M1" > + [(set_attr "type" "csel")] > +) > + > (define_insn "csneg3<mode>_insn" > [(set (match_operand:GPI 0 "register_operand" "=r") > (if_then_else:GPI > diff --git a/gcc/testsuite/gcc.target/aarch64/csneg-1.c b/gcc/testsuite/gcc.target/aarch64/csneg-1.c > index 29d4e4e..4860d64 100644 > --- a/gcc/testsuite/gcc.target/aarch64/csneg-1.c > +++ b/gcc/testsuite/gcc.target/aarch64/csneg-1.c > @@ -56,3 +56,15 @@ int test_csneg_cmp(int x) > x = -x; > return x; > } > + > +unsigned long long > +test_csneg_uxtw (unsigned int a, > + unsigned int b, > + unsigned int c) > +{ > + /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*ne" } } */ > + /* { dg-final { scan-assembler-not "uxtw\tw\[0-9\]*.*" } } */ > + unsigned int val; > + val = a ? b: -c; > + return val; > +} >
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index c3cd58d..373f2d5 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -3132,6 +3132,18 @@ [(set_attr "type" "csel")] ) +(define_insn "csneg3_uxtw_insn" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (if_then_else:SI + (match_operand 1 "aarch64_comparison_operation" "") + (neg:SI (match_operand:SI 2 "register_operand" "r")) + (match_operand:SI 3 "aarch64_reg_or_zero" "rZ"))))] + "" + "csneg\\t%w0, %w3, %w2, %M1" + [(set_attr "type" "csel")] +) + (define_insn "csneg3<mode>_insn" [(set (match_operand:GPI 0 "register_operand" "=r") (if_then_else:GPI diff --git a/gcc/testsuite/gcc.target/aarch64/csneg-1.c b/gcc/testsuite/gcc.target/aarch64/csneg-1.c index 29d4e4e..4860d64 100644 --- a/gcc/testsuite/gcc.target/aarch64/csneg-1.c +++ b/gcc/testsuite/gcc.target/aarch64/csneg-1.c @@ -56,3 +56,15 @@ int test_csneg_cmp(int x) x = -x; return x; } + +unsigned long long +test_csneg_uxtw (unsigned int a, + unsigned int b, + unsigned int c) +{ + /* { dg-final { scan-assembler "csneg\tw\[0-9\]*.*ne" } } */ + /* { dg-final { scan-assembler-not "uxtw\tw\[0-9\]*.*" } } */ + unsigned int val; + val = a ? b: -c; + return val; +}
Hi all, This is a simple patch to add csneg3_uxtw_insn into aarch64 backend. It will save one uxtw instruction as a write to the 32-bit w-register implicitly zero-extends the value up to the full 64 bits of an x-register. aarch64-none-elf regression test Okay without any issues. Okay to commit? Regards, Renlin Li gcc/ChangeLog: 2015-10-02 Renlin Li <renlin.li@arm.com> * config/aarch64/aarch64.md (csneg3_uxtw_insn): New pattern. gcc/testsuite/ChangeLog: 2015-10-02 Renlin Li <renlin.li@arm.com> * gcc.target/aarch64/csneg-1.c: Update test.