[RFC,3/4] hw/intc/arm_gicv3_kvm: Implement get/put functions

diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index b48f78f..5f268a3 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -21,8 +21,10 @@ 
 
 #include "hw/intc/arm_gicv3_common.h"
 #include "hw/sysbus.h"
+#include "qemu/error-report.h"
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
+#include "gicv3_internal.h"
 #include "vgic_common.h"
 
 #ifdef DEBUG_GICV3_KVM
@@ -41,6 +43,15 @@ 
 #define KVM_ARM_GICV3_GET_CLASS(obj) \
      OBJECT_GET_CLASS(KVMARMGICv3Class, (obj), TYPE_KVM_ARM_GICV3)
 
+#define ICC_PMR_EL1     ARM64_SYS_REG(0b11, 0b000, 0b0100, 0b0110, 0b000)
+#define ICC_BPR0_EL1    ARM64_SYS_REG(0b11, 0b000, 0b1100, 0b1000, 0b011)
+#define ICC_APR0_EL1(n) ARM64_SYS_REG(0b11, 0b000, 0b1100, 0b1000, 0b100 | n)
+#define ICC_APR1_EL1(n) ARM64_SYS_REG(0b11, 0b000, 0b1100, 0b1001, 0b000 | n)
+#define ICC_BPR1_EL1    ARM64_SYS_REG(0b11, 0b000, 0b1100, 0b1100, 0b011)
+#define ICC_CTLR_EL1    ARM64_SYS_REG(0b11, 0b000, 0b1100, 0b1100, 0b100)
+#define ICC_IGRPEN0_EL1 ARM64_SYS_REG(0b11, 0b000, 0b1100, 0b1100, 0b110)
+#define ICC_IGRPEN1_EL1 ARM64_SYS_REG(0b11, 0b000, 0b1100, 0b1100, 0b111)
+
 typedef struct KVMARMGICv3Class {
     ARMGICv3CommonClass parent_class;
     DeviceRealize parent_realize;
@@ -54,16 +65,382 @@  static void kvm_arm_gicv3_set_irq(void *opaque, int irq, int level)
     kvm_arm_gic_set_irq(s->num_irq, irq, level);
 }
 
+#define KVM_VGIC_ATTR(offset, cpu) \
+    ((((uint64_t)(cpu) << KVM_DEV_ARM_VGIC_CPUID_SHIFT) & \
+      KVM_DEV_ARM_VGIC_CPUID_MASK) | \
+     (((uint64_t)(offset) << KVM_DEV_ARM_VGIC_OFFSET_SHIFT) & \
+      KVM_DEV_ARM_VGIC_OFFSET_MASK))
+
+static inline void kvm_gicd_access(GICv3State *s, int offset, int cpu,
+                                   uint32_t *val, bool write)
+{
+    kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
+                      KVM_VGIC_ATTR(offset, cpu), val, write);
+}
+
+static inline void kvm_gicr_access(GICv3State *s, int offset, int cpu,
+                                   uint32_t *val, bool write)
+{
+    kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
+                      KVM_VGIC_ATTR(offset, cpu), val, write);
+}
+
+static inline void kvm_gicc_access(GICv3State *s, uint64_t reg, int cpu,
+                                   uint64_t *val, bool write)
+{
+    kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_REGS,
+                      ((((uint64_t)(cpu) << KVM_DEV_ARM_VGIC_CPUID_SHIFT) &
+                        KVM_DEV_ARM_VGIC_CPUID_MASK) | reg), val, write);
+}
+
+/*
+ * Translate from the in-kernel field for an IRQ value to/from the qemu
+ * representation.
+ */
+typedef void (*vgic_translate_fn)(GICv3State *s, int irq, int cpu,
+                                  uint32_t *field, bool to_kernel);
+
+/* synthetic translate function used for clear/set registers to completely
+ * clear a setting using a clear-register before setting the remaining bits
+ * using a set-register */
+static void translate_clear(GICv3State *s, int irq, int cpu,
+                            uint32_t *field, bool to_kernel)
+{
+    if (to_kernel) {
+        *field = ~0;
+    } else {
+        /* does not make sense: qemu model doesn't use set/clear regs */
+        abort();
+    }
+}
+
+static void translate_enabled(GICv3State *s, int irq, int cpu,
+                              uint32_t *field, bool to_kernel)
+{
+    if (to_kernel) {
+        *field = test_bit(cpu, s->irq_state[irq].enabled);
+    } else {
+        set_irq_bit(s, s->irq_state[irq].enabled, irq, cpu, *field);
+    }
+}
+
+static void translate_group(GICv3State *s, int irq, int cpu,
+                            uint32_t *field, bool to_kernel)
+{
+    if (to_kernel) {
+        *field = test_bit(cpu, s->irq_state[irq].group);
+    } else {
+        set_irq_bit(s, s->irq_state[irq].group, irq, cpu, *field);
+    }
+}
+
+static void translate_trigger(GICv3State *s, int irq, int cpu,
+                              uint32_t *field, bool to_kernel)
+{
+    if (to_kernel) {
+        *field = s->irq_state[irq].edge_trigger ? 2 : 0;
+    } else {
+        s->irq_state[irq].edge_trigger = (*field & 2) ? true : false;
+    }
+}
+
+static void translate_pending(GICv3State *s, int irq, int cpu,
+                              uint32_t *field, bool to_kernel)
+{
+    if (to_kernel) {
+        *field = gicv3_test_pending(s, irq, cpu);
+    } else {
+        set_irq_bit(s, s->irq_state[irq].pending, irq, cpu, *field);
+        /* TODO: Capture if level-line is held high in the kernel */
+    }
+}
+
+static void translate_active(GICv3State *s, int irq, int cpu,
+                             uint32_t *field, bool to_kernel)
+{
+    if (to_kernel) {
+        *field = test_bit(cpu, s->irq_state[irq].active);
+    } else {
+        set_irq_bit(s, s->irq_state[irq].active, irq, cpu, *field);
+    }
+}
+
+static void translate_priority(GICv3State *s, int irq, int cpu,
+                               uint32_t *field, bool to_kernel)
+{
+    GICv3CPUState *c = &s->cpu[cpu];
+
+    if (to_kernel) {
+        *field = GIC_GET_PRIORITY(irq);
+    } else {
+        GIC_SET_PRIORITY(irq, *field);
+    }
+}
+
+#define for_each_irq_reg(_irq, _max, _field_width) \
+    for (_irq = 0; _irq < _max; _irq += (32 / _field_width))
+
+/* Read a register group from the kernel VGIC */
+static void kvm_dist_get(GICv3State *s, uint32_t offset, int width,
+                         vgic_translate_fn translate_fn)
+{
+    uint32_t reg;
+    int j;
+    int irq, cpu, maxcpu;
+    uint32_t field;
+    int regsz = 32 / width; /* irqs per kernel register */
+
+    for_each_irq_reg(irq, s->num_irq, width) {
+        maxcpu = irq < GIC_INTERNAL ? s->num_cpu : 1;
+        for (cpu = 0; cpu < maxcpu; cpu++) {
+            /* In GICv3 SGI/PPIs are stored in redistributor
+             * Offsets in SGI area are the same as in distributor
+             */
+            if (irq < GIC_INTERNAL) {
+                kvm_gicr_access(s, offset + GICR_SGI_OFFSET, cpu, &reg, false);
+            } else {
+                kvm_gicd_access(s, offset, cpu, &reg, false);
+            }
+            for (j = 0; j < regsz; j++) {
+                field = extract32(reg, j * width, width);
+                translate_fn(s, irq + j, cpu, &field, false);
+            }
+        }
+        offset += 4;
+    }
+}
+
+/* Write a register group to the kernel VGIC */
+static void kvm_dist_put(GICv3State *s, uint32_t offset, int width,
+                         vgic_translate_fn translate_fn)
+{
+    uint32_t reg;
+    int j;
+    int irq, cpu, maxcpu;
+    uint32_t field;
+    int regsz = 32 / width; /* irqs per kernel register */
+
+    for_each_irq_reg(irq, s->num_irq, width) {
+        maxcpu = irq < GIC_INTERNAL ? s->num_cpu : 1;
+        for (cpu = 0; cpu < maxcpu; cpu++) {
+            reg = 0;
+            for (j = 0; j < regsz; j++) {
+                translate_fn(s, irq + j, cpu, &field, true);
+                reg = deposit32(reg, j * width, width, field);
+            }
+            /* In GICv3 SGI/PPIs are stored in redistributor
+             * Offsets in SGI area are the same as in distributor
+             */
+            if (irq < GIC_INTERNAL) {
+                kvm_gicr_access(s, offset + GICR_SGI_OFFSET, cpu, &reg, true);
+            } else {
+                kvm_gicd_access(s, offset, cpu, &reg, true);
+            }
+        }
+        offset += 4;
+    }
+}
+
+static void kvm_arm_gicv3_check(GICv3State *s)
+{
+    uint32_t reg, num_irq;
+
+    /* Sanity checking s->num_irq */
+    kvm_gicd_access(s, GICD_TYPER, 0, &reg, false);
+    num_irq = ((reg & 0x1f) + 1) * 32;
+
+    if (num_irq < s->num_irq) {
+        error_report("Model requests %u IRQs, but kernel supports max %u\n",
+                     s->num_irq, num_irq);
+        abort();
+    }
+
+    /* TODO: Consider checking compatibility with the IIDR ? */
+}
+
 static void kvm_arm_gicv3_put(GICv3State *s)
 {
-    /* TODO */
-    DPRINTF("Cannot put kernel gic state, no kernel interface\n");
+    int ncpu, i;
+
+    kvm_arm_gicv3_check(s);
+
+    /*****************************************************************
+     * (Re)distributor State
+     */
+
+    kvm_gicd_access(s, GICD_CTLR, 0, &s->ctlr, true);
+
+    for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
+        GICv3CPUState *c = &s->cpu[ncpu];
+        uint32_t reg = c->cpu_enabled ? 0 : GICR_WAKER_ProcessorSleep;
+
+        kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, true);
+    }
+
+    /* irq_state[n].enabled -> GICD_ISENABLERn */
+    kvm_dist_put(s, GICD_ICENABLER, 1, translate_clear);
+    kvm_dist_put(s, GICD_ISENABLER, 1, translate_enabled);
+
+    /* irq_state[n].group -> GICD_IGROUPRn */
+    kvm_dist_put(s, GICD_IGROUPR, 1, translate_group);
+
+    /* Restore targets before pending to ensure the pending state is set on
+     * the appropriate CPU interfaces in the kernel */
+
+    /* s->route[irq] -> GICD_IROUTERn */
+    for (i = GIC_INTERNAL; i < s->num_irq; i++) {
+        uint64_t reg;
+        uint32_t offset = GICD_IROUTER + (sizeof(reg) * i);
+
+        reg = s->irq_route[i - GIC_INTERNAL];
+        kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
+                          KVM_DEV_ARM_VGIC_64BIT | KVM_VGIC_ATTR(offset, 0),
+                          &reg, true);
+    }
+
+    /* irq_state[n].trigger -> GICD_ICFGRn
+     * (restore configuration registers before pending IRQs so we treat
+     * level/edge correctly) */
+    kvm_dist_put(s, GICD_ICFGR, 2, translate_trigger);
+
+    /* irq_state[n].pending + irq_state[n].level -> GICD_ISPENDRn */
+    kvm_dist_put(s, GICD_ICPENDR, 1, translate_clear);
+    kvm_dist_put(s, GICD_ISPENDR, 1, translate_pending);
+
+    /* irq_state[n].active -> GICD_ISACTIVERn */
+    kvm_dist_put(s, GICD_ICACTIVER, 1, translate_clear);
+    kvm_dist_put(s, GICD_ISACTIVER, 1, translate_active);
+
+    /* s->priorityX[irq] -> ICD_IPRIORITYRn */
+    kvm_dist_put(s, GICD_IPRIORITYR, 8, translate_priority);
+
+    /*****************************************************************
+     * CPU Interface(s) State
+     */
+
+    for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
+        GICv3CPUState *c = &s->cpu[ncpu];
+        uint64_t reg;
+
+        reg = c->ctlr[1] & (ICC_CTLR_CBPR | ICC_CTLR_EOIMODE | ICC_CTLR_PMHE);
+        kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, &reg, true);
+
+        reg = gicv3_get_igrpen0(s, ncpu);
+        kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, &reg, true);
+
+        reg = gicv3_get_igrpen1(s, ncpu);
+        kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, &reg, true);
+
+        reg = c->priority_mask;
+        kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &reg, true);
+
+        reg = c->bpr[0];
+        kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &reg, true);
+
+        reg = c->bpr[1];
+        kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &reg, true);
+
+        for (i = 0; i < 4; i++) {
+            reg = c->apr[i][0];
+            kvm_gicc_access(s, ICC_APR0_EL1(i), ncpu, &reg, true);
+        }
+
+        for (i = 0; i < 4; i++) {
+            reg = c->apr[i][1];
+            kvm_gicc_access(s, ICC_APR1_EL1(i), ncpu, &reg, true);
+        }
+    }
 }
 
 static void kvm_arm_gicv3_get(GICv3State *s)
 {
-    /* TODO */
-    DPRINTF("Cannot get kernel gic state, no kernel interface\n");
+    int ncpu, i;
+
+    kvm_arm_gicv3_check(s);
+
+    /*****************************************************************
+     * (Re)distributor State
+     */
+
+    /* GICD_CTLR -> s->ctlr */
+    kvm_gicd_access(s, GICD_CTLR, 0, &s->ctlr, false);
+
+    for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
+        GICv3CPUState *c = &s->cpu[ncpu];
+        uint32_t reg;
+
+        kvm_gicr_access(s, GICR_WAKER, ncpu, &reg, false);
+        c->cpu_enabled = !(reg & GICR_WAKER_ProcessorSleep);
+    }
+
+    /* GICD_IIDR -> ? */
+    /* kvm_gicd_access(s, GICD_IIDR, 0, &reg, false); */
+
+    /* GICD_IGROUPRn -> irq_state[n].group */
+    kvm_dist_get(s, GICD_IGROUPR, 1, translate_group);
+
+    /* GICD_ISENABLERn -> irq_state[n].enabled */
+    kvm_dist_get(s, GICD_ISENABLER, 1, translate_enabled);
+
+    /* GICD_ISPENDRn -> irq_state[n].pending + irq_state[n].level */
+    kvm_dist_get(s, GICD_ISPENDR, 1, translate_pending);
+
+    /* GICD_ISACTIVERn -> irq_state[n].active */
+    kvm_dist_get(s, GICD_ISACTIVER, 1, translate_active);
+
+    /* GICD_ICFRn -> irq_state[n].trigger */
+    kvm_dist_get(s, GICD_ICFGR, 2, translate_trigger);
+
+    /* GICD_IPRIORITYRn -> s->priorityX[irq] */
+    kvm_dist_get(s, GICD_IPRIORITYR, 8, translate_priority);
+
+    /* GICD_IROUTERn -> s->route[irq] */
+    for (i = GIC_INTERNAL; i < s->num_irq; i++) {
+        uint64_t reg;
+        uint32_t offset = GICD_IROUTER + (sizeof(reg) * i);
+
+        kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS,
+                          KVM_DEV_ARM_VGIC_64BIT | KVM_VGIC_ATTR(offset, 0),
+                          &reg, false);
+        s->irq_route[i - GIC_INTERNAL] = reg;
+    }
+
+    /*****************************************************************
+     * CPU Interface(s) State
+     */
+
+    for (ncpu = 0; ncpu < s->num_cpu; ncpu++) {
+        GICv3CPUState *c = &s->cpu[ncpu];
+        uint64_t reg;
+
+        kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, &reg, false);
+        c->ctlr[1] = reg & (ICC_CTLR_CBPR | ICC_CTLR_EOIMODE | ICC_CTLR_PMHE);
+
+        kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, &reg, false);
+        gicv3_set_igrpen0(s, ncpu, reg);
+
+        kvm_gicc_access(s, ICC_IGRPEN1_EL1, ncpu, &reg, false);
+        gicv3_set_igrpen1(s, ncpu, reg);
+
+        kvm_gicc_access(s, ICC_PMR_EL1, ncpu, &reg, false);
+        c->priority_mask = reg & ICC_PMR_PRIORITY_MASK;
+
+        kvm_gicc_access(s, ICC_BPR0_EL1, ncpu, &reg, false);
+        c->bpr[0] = reg & ICC_BPR_BINARYPOINT_MASK;
+
+        kvm_gicc_access(s, ICC_BPR1_EL1, ncpu, &reg, false);
+        c->bpr[1] = reg & ICC_BPR_BINARYPOINT_MASK;
+
+        for (i = 0; i < 4; i++) {
+            kvm_gicc_access(s, ICC_APR0_EL1(i), ncpu, &reg, false);
+            c->apr[i][0] = reg;
+        }
+
+        for (i = 0; i < 4; i++) {
+            kvm_gicc_access(s, ICC_APR1_EL1(i), ncpu, &reg, false);
+            c->apr[i][1] = reg;
+        }
+    }
 }
 
 static void kvm_arm_gicv3_reset(DeviceState *dev)
@@ -74,6 +451,12 @@  static void kvm_arm_gicv3_reset(DeviceState *dev)
     DPRINTF("Reset\n");
 
     kgc->parent_reset(dev);
+
+    if (!kvm_device_check_attr(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_DIST_REGS, 0)) {
+        DPRINTF("Cannot put kernel gic state, no kernel interface\n");
+        return;
+    }
+
     kvm_arm_gicv3_put(s);
 }