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Wed, 30 Sep 2015 09:13:24 -0700 From: Adrian Alonso To: , , , , CC: , , , , , , , , Subject: [PATCH v8 7/7] pinctrl: freescale: imx: imx7d iomuxc-lpsr devicetree bindings Date: Wed, 30 Sep 2015 11:11:09 -0500 Message-ID: <1443629469-12294-7-git-send-email-aalonso@freescale.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1443629469-12294-1-git-send-email-aalonso@freescale.com> References: <1443629469-12294-1-git-send-email-aalonso@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BY2FFO11FD004; 1:3lIbsXRxRMDAFwybYl98uWu5P8zUKGApcfSuRXKvDlI0MRXEzm9eTuD5EPdHPyVbkls9fWRuSLNoGxxhXU2vs9ERzeM+2uIQUuDkrQZeJP66WjVTFHSSf4sFePxjd/vT8aGQ7KpOfJxSOOx6CVsRu3o/KjR5WrhTjILjgBnMRuAw0FtMC77tbO/CNdOGJncOio1R6iHSjj82xeDxoneY8u1U0Q4UcGpvse1ecn9ebS91/sbIHeg/5IOLZrkEF4lJIIEgudawuu7S5AYExXgRGPWJoPRph3Ox4eAu+BnxphUXzu41PR0g9/M6lajLnC/Ot1Z3+TZNvhgh1iCBDh7FYq+5EGrspfTDqg3fjmWzbLPYxuGS0NF0HfgRmtJVBsUgqQWO3yo3FzROwxwdYbhDBQ== X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:NLI; 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CY1PR0301MB0778; 5:33ngNXz4HrxzWa+oRIb6MXrNqUTIpe2Mqv0l6iHJuLSaZ9v71/Co/QvGGVOb2hl7ijA2fX+q5GRli/YQKBFv5BW0FW7lghVw3Ns0AL7TIooGOXiZeU6bXSjXR9SGVBqFv1/1mznpBpK4C56+8T4Rdw==; 24:Hk26/Hj+LJtAMLCqT0J6YSht+vScV22s5cFSbiVY0kjN4/c29/XXL6Cutr7IZk7Lfi/Ndj8SiVX+uLod80E4PyZAjk7ExkMT4/hJ5OwKg3s=; 20:+GLD1Ax7SdivMDN/jV2R41Q78bw1Drmc9QTv7qiNHrseDWVKlHt/HcgjvvoBWA9F08J1Tz50Xn4RT76KqiZbCg== X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2015 16:13:25.9348 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB0778 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add iomuxc-lpsr devicetree bindings documentation Provide documentation context as well an example on pheriperals that could use pad from either iomuxc controller supported by iMX7D SoC Signed-off-by: Adrian Alonso --- Changes for V2: New patch on imx7d iomuxc-lpsr patch series Changes for V3: Add shared input select register notes Changes for V4: Resend Changes for V5: - Fix spell error - Remove references of SHARE_INPUT_SELECT_REG flag Changes for V6: Resend Changes for V7: Resend Changes for V8: Correct SDA pad example .../bindings/pinctrl/fsl,imx7d-pinctrl.txt | 63 +++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt index 8bbf25d..457b2c6 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt @@ -1,16 +1,42 @@ * Freescale i.MX7 Dual IOMUX Controller +iMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar +as previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low +power state retention capabilities on gpios that are part of iomuxc-lpsr +(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for +mux and pad control settings, it shares the input select register from main +iomuxc controller for daisy chain settings, the fsl,input-sel property extends +fsl,imx-pinctrl driver to support iomuxc-lpsr controller. + +iomuxc_lpsr: iomuxc-lpsr@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; +}; + +iomuxc: iomuxc@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; +}; + +Pheriparials using pads from iomuxc-lpsr support low state retention power +state, under LPSR mode GPIO's state of pads are retain. + Please refer to fsl,imx-pinctrl.txt in this directory for common binding part and usage. Required properties: -- compatible: "fsl,imx7d-iomuxc" +- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or + "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller. - fsl,pins: each entry consists of 6 integers and represents the mux and config setting for one pin. The first 5 integers are specified using a PIN_FUNC_ID macro, which can be found in imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual Reference Manual for detailed CONFIG settings. +- fsl,input-sel: required property for iomuxc-lpsr controller, this property is + a phandle for main iomuxc controller which shares the input select register for + daisy chain settings. CONFIG bits definition: PAD_CTL_PUS_100K_DOWN (0 << 5) @@ -25,3 +51,38 @@ PAD_CTL_DSE_X1 (0 << 0) PAD_CTL_DSE_X2 (1 << 0) PAD_CTL_DSE_X3 (2 << 0) PAD_CTL_DSE_X4 (3 << 0) + +Examples: +While iomuxc-lpsr is intended to be used by dedicated peripherals to take +advantages of LPSR power mode, is also possible that an IP to use pads from +any of the iomux controllers. For example the I2C1 IP can use SCL pad from +iomuxc-lpsr controller and SDA pad from iomuxc controller as: + +i2c1: i2c@30a20000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>; + status = "okay"; +}; + +iomuxc-lpsr@302c0000 { + compatible = "fsl,imx7d-iomuxc-lpsr"; + reg = <0x302c0000 0x10000>; + fsl,input-sel = <&iomuxc>; + + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f + >; + }; +}; + +iomuxc@30330000 { + compatible = "fsl,imx7d-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + >; + }; +};