diff mbox

[AArch64] Fix Prefetch ICE

Message ID SN2PR0701MB102479B3E836A672A4A0CE388E430@SN2PR0701MB1024.namprd07.prod.outlook.com
State New
Headers show

Commit Message

Hurugalawadi, Naveen Sept. 24, 2015, 6:47 a.m. UTC 
Hi,

Please find attached the patch that fixes an ICE for prefetch.

The predicate is too lose for the constraints. Hence, the patch tightens
up the predicate to be exactly as constraint  allows, avoids a “reload”
and allows better code generation.
 
Submitted on behalf of Andrew Pinski.

Thanks,
Naveen

2015-09-24  Andrew Pinski  <apinski@cavium.com>    

ChangeLog

	* config/aarch64/aarch64.md (prefetch):
	Change the predicate of operand 0 to register_operand.

Comments

Marcus Shawcroft Sept. 24, 2015, 11:13 a.m. UTC | #1 
On 24 September 2015 at 07:47, Hurugalawadi, Naveen
<Naveen.Hurugalawadi@caviumnetworks.com> wrote:
> Hi,
>
> Please find attached the patch that fixes an ICE for prefetch.
>
> The predicate is too lose for the constraints. Hence, the patch tightens
> up the predicate to be exactly as constraint  allows, avoids a “reload”
> and allows better code generation.
>
> Submitted on behalf of Andrew Pinski.
>
> Thanks,
> Naveen
>
> 2015-09-24  Andrew Pinski  <apinski@cavium.com>
>
> ChangeLog
>
>         * config/aarch64/aarch64.md (prefetch):
>         Change the predicate of operand 0 to register_operand.

Hi, OK and can you back port to 5 ? Thanks /Marcus
diff mbox

Patch

Index: config/aarch64/aarch64.md
===================================================================
--- config/aarch64/aarch64.md	(revision 228072)
+++ config/aarch64/aarch64.md	(working copy)
@@ -466,7 +466,7 @@ 
 )
 
 (define_insn "prefetch"
-  [(prefetch (match_operand:DI 0 "address_operand" "r")
+  [(prefetch (match_operand:DI 0 "register_operand" "r")
             (match_operand:QI 1 "const_int_operand" "")
             (match_operand:QI 2 "const_int_operand" ""))]
   ""