powerpc/e6500: add TMCFG0 register definition
diff mbox

Message ID 5602BFEE.7060708@freescale.com
State Accepted
Headers show

Commit Message

Tudor Laurentiu Sept. 23, 2015, 3:06 p.m. UTC
The register is not currently used in the base kernel
but will be in a forthcoming kvm patch.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
---
 arch/powerpc/include/asm/reg_booke.h | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Scott Wood Sept. 24, 2015, 10:18 p.m. UTC | #1
On Wed, 2015-09-23 at 18:06 +0300, Laurentiu Tudor wrote:
> The register is not currently used in the base kernel
> but will be in a forthcoming kvm patch.
> 
> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
> ---
>  arch/powerpc/include/asm/reg_booke.h | 6 ++++++
>  1 file changed, 6 insertions(+)

Acked-by: Scott Wood <scottwood@freescale.com>

-Scott

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Paul Mackerras Oct. 15, 2015, 5:29 a.m. UTC | #2
On Wed, Sep 23, 2015 at 06:06:22PM +0300, Laurentiu Tudor wrote:
> The register is not currently used in the base kernel
> but will be in a forthcoming kvm patch.
> 
> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>

Thanks, applied to my kvm-ppc-next branch.

Paul.
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Patch
diff mbox

diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index 16547ef..2fef74b 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -742,6 +742,12 @@ 
 #define MMUBE1_VBE4		0x00000002
 #define MMUBE1_VBE5		0x00000001
 
+#define TMRN_TMCFG0      16	/* Thread Management Configuration Register 0 */
+#define TMRN_TMCFG0_NPRIBITS       0x003f0000 /* Bits of thread priority */
+#define TMRN_TMCFG0_NPRIBITS_SHIFT 16
+#define TMRN_TMCFG0_NATHRD         0x00003f00 /* Number of active threads */
+#define TMRN_TMCFG0_NATHRD_SHIFT   8
+#define TMRN_TMCFG0_NTHRD          0x0000003f /* Number of threads */
 #define TMRN_IMSR0	0x120	/* Initial MSR Register 0 (e6500) */
 #define TMRN_IMSR1	0x121	/* Initial MSR Register 1 (e6500) */
 #define TMRN_INIA0	0x140	/* Next Instruction Address Register 0 */