diff mbox

[v3,06/25] target-arm: Add condexec state to insn_start

Message ID 1442953507-4074-7-git-send-email-rth@twiddle.net
State New
Headers show

Commit Message

Richard Henderson Sept. 22, 2015, 8:24 p.m. UTC 
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target-arm/cpu.h           | 1 +
 target-arm/translate-a64.c | 2 +-
 target-arm/translate.c     | 3 ++-
 3 files changed, 4 insertions(+), 2 deletions(-)
diff mbox

Patch

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1b80516..c4a7400 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -97,6 +97,7 @@ 
 struct arm_boot_info;
 
 #define NB_MMU_MODES 7
+#define TARGET_INSN_START_EXTRA_WORDS 1
 
 /* We currently assume float and double are IEEE single and double
    precision respectively.
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index bc2040e..654a586 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -11090,7 +11090,7 @@  void gen_intermediate_code_internal_a64(ARMCPU *cpu,
             tcg_ctx.gen_opc_instr_start[lj] = 1;
             tcg_ctx.gen_opc_icount[lj] = num_insns;
         }
-        tcg_gen_insn_start(dc->pc);
+        tcg_gen_insn_start(dc->pc, 0);
         num_insns++;
 
         if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 44468dc..fb69ecb 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11317,7 +11317,8 @@  static inline void gen_intermediate_code_internal(ARMCPU *cpu,
             tcg_ctx.gen_opc_instr_start[lj] = 1;
             tcg_ctx.gen_opc_icount[lj] = num_insns;
         }
-        tcg_gen_insn_start(dc->pc);
+        tcg_gen_insn_start(dc->pc,
+                           (dc->condexec_cond << 4) | (dc->condexec_mask >> 1));
         num_insns++;
 
 #ifdef CONFIG_USER_ONLY