From patchwork Tue Sep 22 15:38:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vishnupatekar X-Patchwork-Id: 521162 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 413C71401AD for ; Wed, 23 Sep 2015 01:41:21 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=sem0lYhD; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933490AbbIVPkT (ORCPT ); Tue, 22 Sep 2015 11:40:19 -0400 Received: from mail-pa0-f54.google.com ([209.85.220.54]:34070 "EHLO mail-pa0-f54.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933428AbbIVPkQ (ORCPT ); Tue, 22 Sep 2015 11:40:16 -0400 Received: by padhy16 with SMTP id hy16so12525902pad.1; Tue, 22 Sep 2015 08:40:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iyUISm2jgsQojciVRfZfZGgr2Y2mMbMnMpHFbBVN8Eg=; b=sem0lYhDshkhQpBPlc2DqUJc3ijJ1szH/oFusdjLJg99wzR2oi5U2lDmz8fkR2nNT8 eKYVnGiUKJTCjvYrgoYNRRU5mgcoMJpbs9v4W3kd9NMHhtJonsFwPTsdq3CZE8umf3gs KWFtti+j3c2PB9SyzlU/CWZ2OiTTtCp7KmUnZNE2A8tC66YOCZl/ALKW6R4ClQXmXY0n DzKNHYVvr4XgxuJDoO/SeS+iKJb1GYeiuzTeI+DWqtb+2xKdhLLHKPnBDrLuN/ETX3Rd ooc8seHF0rTkcvc/F4GiHxrD6/BC/TTntzmQ+0gw+WeB1O40oU0u5d+bF1/nEUPaCZv5 MRCA== X-Received: by 10.66.219.227 with SMTP id pr3mr32191645pac.33.1442936415613; Tue, 22 Sep 2015 08:40:15 -0700 (PDT) Received: from localhost.localdomain ([116.88.137.3]) by smtp.gmail.com with ESMTPSA id li11sm2957907pab.43.2015.09.22.08.40.10 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 22 Sep 2015 08:40:14 -0700 (PDT) From: Vishnu Patekar To: robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, maxime.ripard@free-electrons.com, linux@arm.linux.org.uk, emilio@elopez.com.ar, linus.walleij@linaro.org Cc: jenskuske@gmail.com, hdegoede@redhat.com, wens@csie.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com, linux-gpio@vger.kernel.org, Vishnu Patekar Subject: [PATCH 3/4] ARM: dts: sun8i: Add Allwinner A83T dtsi Date: Tue, 22 Sep 2015 23:38:56 +0800 Message-Id: <1442936337-3104-4-git-send-email-vishnupatekar0510@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1442936337-3104-1-git-send-email-vishnupatekar0510@gmail.com> References: <1442936337-3104-1-git-send-email-vishnupatekar0510@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Allwinner A83T is new octa-core cortex-a7 SOC. This adds the basic dtsi, the clocks differs from earlier sun8i SOCs. Signed-off-by: Vishnu Patekar --- arch/arm/boot/dts/sun8i-a83t.dtsi | 243 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 243 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-a83t.dtsi diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi new file mode 100644 index 0000000..f6ddd9c --- /dev/null +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -0,0 +1,243 @@ +/* + * Copyright 2015 Vishnu Patekar + * + * Vishnu Patekar + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + + */ + +#include "skeleton.dtsi" + +#include + +#include + +/ { + interrupt-parent = <&gic>; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + }; + + cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + }; + + cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <2>; + }; + + cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <3>; + }; + cpu@4 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <4>; + }; + + cpu@5 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <5>; + }; + cpu@6 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <6>; + }; + + cpu@7 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <7>; + }; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + arm,cpu-registers-not-fw-configured; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + soc@01c00000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pio: pinctrl@01c20800 { + compatible = "allwinner,sun8i-a83t-pinctrl"; + interrupts = , + , + ; + /* compatible gets set in SoC specific dtsi file */ + reg = <0x01c20800 0x400>; + /* interrupts get set in SoC specific dtsi file */ + clocks = <&osc24M>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <3>; + #gpio-cells = <3>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PF2", "PF4"; + allwinner,function = "uart0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0", "PF1", "PF2", + "PF3", "PF4", "PF5"; + allwinner,function = "mmc0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0", "PG1", "PG2", + "PG3", "PG4", "PG5"; + allwinner,function = "mmc1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + mmc2_8bit_pins: mmc2_8bit { + allwinner,pins = "PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", + "PC12", "PC13", "PC14", + "PC15"; + allwinner,function = "mmc2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PH0", "PH1"; + allwinner,function = "i2c0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PH2", "PH3"; + allwinner,function = "i2c1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PH4", "PH5"; + allwinner,function = "i2c2"; + allwinner,drive = ; + allwinner,pull = ; + }; + }; + + uart0: serial@01c28000 { + compatible = "snps,dw-apb-uart"; + reg = <0x01c28000 0x400>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, + <0x01c82000 0x1000>, + <0x01c84000 0x2000>, + <0x01c86000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = ; + }; + + }; +};