diff mbox

[PULL,08/10] target-mips: add missing restriction in DAUI instruction

Message ID 1442575535-4735-9-git-send-email-leon.alrae@imgtec.com
State New
Headers show

Commit Message

Leon Alrae Sept. 18, 2015, 11:25 a.m. UTC 
rs cannot be the zero register, Reserved Instruction exception must be
signalled for this case.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-mips/translate.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
diff mbox

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index cd0cf8b..0883782 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -19525,7 +19525,9 @@  static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
 #if defined(TARGET_MIPS64)
             /* OPC_DAUI */
             check_mips_64(ctx);
-            if (rt != 0) {
+            if (rs == 0) {
+                generate_exception(ctx, EXCP_RI);
+            } else if (rt != 0) {
                 TCGv t0 = tcg_temp_new();
                 gen_load_gpr(t0, rs);
                 tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);