diff mbox

[AArch64,2/5] Add BIC instruction.

Message ID 55FAED10.2010108@foss.arm.com
State New
Headers show

Commit Message

Matthew Wahab Sept. 17, 2015, 4:40 p.m. UTC 
Hello,

ARMv8.1 adds atomic swap and atomic load-operate instructions with
optional memory ordering specifiers. This patch adds an expander to
generate a BIC instruction that can be explicitly called when
implementing the atomic_<op>_fetch pattern to calculate the value to
be returned by the operation.

Tested the series for aarch64-none-linux-gnu with native bootstrap and
make check. Also tested for aarch64-none-elf with cross-compiled
check-gcc on an ARMv8.1 emulator with +lse enabled by default.

Ok for trunk?
Matthew

2015-09-17  Matthew Wahab  <matthew.wahab@arm.com>

	* config/aarch64/aarch64.md (bic_<SHIFT:optab><mode>3): New.

Comments

James Greenhalgh Sept. 18, 2015, 8:05 a.m. UTC | #1 
On Thu, Sep 17, 2015 at 05:40:48PM +0100, Matthew Wahab wrote:
> Hello,
> 
> ARMv8.1 adds atomic swap and atomic load-operate instructions with
> optional memory ordering specifiers. This patch adds an expander to
> generate a BIC instruction that can be explicitly called when
> implementing the atomic_<op>_fetch pattern to calculate the value to
> be returned by the operation.
> 
> Tested the series for aarch64-none-linux-gnu with native bootstrap and
> make check. Also tested for aarch64-none-elf with cross-compiled
> check-gcc on an ARMv8.1 emulator with +lse enabled by default.
> 
> Ok for trunk?

Why not make the "*<LOGICAL:optab>_one_cmpl_<SHIFT:optab><mode>3" pattern
named (remove the leading *) and call that in your atomic_<op>_fetch
patterns as:

  and_one_cmpl_<shift><mode>3

I'd rather that than to add a pettern that simply expands to the same
thing.

Thanks,
James

> 
> 2015-09-17  Matthew Wahab  <matthew.wahab@arm.com>
> 
> 	* config/aarch64/aarch64.md (bic_<SHIFT:optab><mode>3): New.
> 
> 

> From 14e122ee98aa20826ee070d20c58c94206cdd91b Mon Sep 17 00:00:00 2001
> From: Matthew Wahab <matthew.wahab@arm.com>
> Date: Mon, 17 Aug 2015 17:48:27 +0100
> Subject: [PATCH 2/5] Add BIC instruction
> 
> Change-Id: Ibef049bfa1bfe5e168feada3dc358f28383e6410
> ---
>  gcc/config/aarch64/aarch64.md | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 88ba72e..bae4af4 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -3351,6 +3351,19 @@
>     (set_attr "simd" "*,yes")]
>  )
>  
> +(define_expand "bic_<SHIFT:optab><mode>3"
> + [(set (match_operand:GPI 0 "register_operand" "=r")
> +   (and:GPI
> +    (not:GPI
> +     (SHIFT:GPI
> +      (match_operand:GPI 1 "register_operand" "r")
> +      (match_operand:QI 2 "aarch64_shift_imm_si" "n")))
> +    (match_operand:GPI 3 "register_operand" "r")))]
> + ""
> + ""
> + [(set_attr "type" "logics_shift_imm")]
> +)
> +
>  (define_insn "*and_one_cmpl<mode>3_compare0"
>    [(set (reg:CC_NZ CC_REGNUM)
>  	(compare:CC_NZ
> -- 
> 2.1.4
>
diff mbox

Patch

From 14e122ee98aa20826ee070d20c58c94206cdd91b Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Mon, 17 Aug 2015 17:48:27 +0100
Subject: [PATCH 2/5] Add BIC instruction

Change-Id: Ibef049bfa1bfe5e168feada3dc358f28383e6410
---
 gcc/config/aarch64/aarch64.md | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 88ba72e..bae4af4 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3351,6 +3351,19 @@ 
    (set_attr "simd" "*,yes")]
 )
 
+(define_expand "bic_<SHIFT:optab><mode>3"
+ [(set (match_operand:GPI 0 "register_operand" "=r")
+   (and:GPI
+    (not:GPI
+     (SHIFT:GPI
+      (match_operand:GPI 1 "register_operand" "r")
+      (match_operand:QI 2 "aarch64_shift_imm_si" "n")))
+    (match_operand:GPI 3 "register_operand" "r")))]
+ ""
+ ""
+ [(set_attr "type" "logics_shift_imm")]
+)
+
 (define_insn "*and_one_cmpl<mode>3_compare0"
   [(set (reg:CC_NZ CC_REGNUM)
 	(compare:CC_NZ
-- 
2.1.4