diff mbox

[U-Boot,v2,11/16] armv8/ls1043ardb: Add nand boot support

Message ID 1442473613-17374-8-git-send-email-Qianyu.Gong@freescale.com
State Superseded
Delegated to: York Sun
Headers show

Commit Message

Gong Qianyu Sept. 17, 2015, 7:06 a.m. UTC 
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
---
 V2:
 -Removed unecessary NAND_PAGE_SIZE in ls1043a_common.h.
 -Fixed "select SUPPORT_SPL" in arch/arm/Kconfig.
 -Used CONFIG_FSL_IFC instead of SPL_NAND_SUPPORT for init_early_memctl_regs() in spl.c
 -Replaced ns_access.h with fsl_csu.h.

 arch/arm/Kconfig                                   |  1 +
 arch/arm/cpu/armv8/fsl-lsch2/Makefile              |  1 +
 arch/arm/cpu/armv8/fsl-lsch2/spl.c                 | 79 ++++++++++++++++++++++
 arch/arm/include/asm/arch-fsl-lsch2/spl.h          |  2 +-
 board/freescale/ls1043ardb/ls1043ardb_pbi.cfg      | 14 ++++
 board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg |  7 ++
 configs/ls1043ardb_nand_defconfig                  |  4 ++
 include/configs/ls1043a_common.h                   | 30 ++++++++
 include/configs/ls1043ardb.h                       | 40 +++++++++++
 9 files changed, 177 insertions(+), 1 deletion(-)

Comments

Scott Wood Sept. 17, 2015, 8:16 p.m. UTC | #1 
On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> 

>  
> +/* NAND SPL */
> +#ifdef CONFIG_NAND_BOOT
> +#define CONFIG_SPL_PBL_PAD
> +#define CONFIG_SPL_FRAMEWORK
> +#define CONFIG_SPL_LDSCRIPT          "arch/arm/cpu/armv8/u-boot-spl.lds"
> +#define CONFIG_SPL_TARGET            "u-boot-with-spl.bin"
> +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> +#define CONFIG_SPL_LIBGENERIC_SUPPORT
> +#define CONFIG_SPL_ENV_SUPPORT
> +#define CONFIG_SPL_WATCHDOG_SUPPORT
> +#define CONFIG_SPL_I2C_SUPPORT
> +#define CONFIG_SPL_SERIAL_SUPPORT
> +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
> +#define CONFIG_SPL_NAND_SUPPORT
> +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> +#define CONFIG_SPL_TEXT_BASE         0x10000000
> +#define CONFIG_SPL_MAX_SIZE          0x1a000
> +#define CONFIG_SPL_STACK             0x1001d000
> +#define CONFIG_SPL_PAD_TO            0x1c000
> +#define CONFIG_SYS_NAND_U_BOOT_OFFS  CONFIG_SPL_PAD_TO
> +#define CONFIG_SYS_NAND_U_BOOT_SIZE  (640 << 10)

You made the U-Boot size be block aligned (assuming 128k block size, which 
the SoC common file should not do), but its offset is not.

-Scott
Gong Qianyu Sept. 18, 2015, 3:36 a.m. UTC | #2 
> -----Original Message-----
> From: Wood Scott-B07421
> Sent: Friday, September 18, 2015 4:16 AM
> To: Gong Qianyu-B52263
> Cc: u-boot@lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> B07421
> Subject: Re: [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support
> 
> On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> >
> 
> >
> > +/* NAND SPL */
> > +#ifdef CONFIG_NAND_BOOT
> > +#define CONFIG_SPL_PBL_PAD
> > +#define CONFIG_SPL_FRAMEWORK
> > +#define CONFIG_SPL_LDSCRIPT          "arch/arm/cpu/armv8/u-boot-
> spl.lds"
> > +#define CONFIG_SPL_TARGET            "u-boot-with-spl.bin"
> > +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> > +#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_ENV_SUPPORT
> > +#define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_I2C_SUPPORT
> > +#define CONFIG_SPL_SERIAL_SUPPORT #define
> > +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
> > +#define CONFIG_SPL_NAND_SUPPORT
> > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > +#define CONFIG_SPL_TEXT_BASE         0x10000000
> > +#define CONFIG_SPL_MAX_SIZE          0x1a000
> > +#define CONFIG_SPL_STACK             0x1001d000
> > +#define CONFIG_SPL_PAD_TO            0x1c000
> > +#define CONFIG_SYS_NAND_U_BOOT_OFFS  CONFIG_SPL_PAD_TO #define
> > +CONFIG_SYS_NAND_U_BOOT_SIZE  (640 << 10)
> 
> You made the U-Boot size be block aligned (assuming 128k block size,
> which the SoC common file should not do), but its offset is not.
> 
> -Scott

Eh, yes. The CONFIG_SPL_PAD_TO should be block aligned and put to board specific file assuming different NAND chips.
That reminds me. SPL and U-Boot size should be block aligned, so it is with the env size. Right?

Regards,
Qianyu
Scott Wood Sept. 18, 2015, 5:14 a.m. UTC | #3 
On Thu, 2015-09-17 at 22:36 -0500, Gong Qianyu-B52263 wrote:
> > -----Original Message-----
> > From: Wood Scott-B07421
> > Sent: Friday, September 18, 2015 4:16 AM
> > To: Gong Qianyu-B52263
> > Cc: u-boot@lists.denx.de; Hu Mingkai-B21284; Sun York-R58495; Hou
> > Zhiqiang-B48286; Song Wenbin-B53747; Xie Shaohui-B21989; Wood Scott-
> > B07421
> > Subject: Re: [Patch v2 11/16] armv8/ls1043ardb: Add nand boot support
> > 
> > On Thu, 2015-09-17 at 15:06 +0800, Gong Qianyu wrote:
> > > 
> > 
> > > 
> > > +/* NAND SPL */
> > > +#ifdef CONFIG_NAND_BOOT
> > > +#define CONFIG_SPL_PBL_PAD
> > > +#define CONFIG_SPL_FRAMEWORK
> > > +#define CONFIG_SPL_LDSCRIPT          "arch/arm/cpu/armv8/u-boot-
> > spl.lds"
> > > +#define CONFIG_SPL_TARGET            "u-boot-with-spl.bin"
> > > +#define CONFIG_SPL_LIBCOMMON_SUPPORT
> > > +#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_ENV_SUPPORT
> > > +#define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_I2C_SUPPORT
> > > +#define CONFIG_SPL_SERIAL_SUPPORT #define
> > > +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
> > > +#define CONFIG_SPL_NAND_SUPPORT
> > > +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
> > > +#define CONFIG_SPL_TEXT_BASE         0x10000000
> > > +#define CONFIG_SPL_MAX_SIZE          0x1a000
> > > +#define CONFIG_SPL_STACK             0x1001d000
> > > +#define CONFIG_SPL_PAD_TO            0x1c000
> > > +#define CONFIG_SYS_NAND_U_BOOT_OFFS  CONFIG_SPL_PAD_TO #define
> > > +CONFIG_SYS_NAND_U_BOOT_SIZE  (640 << 10)
> > 
> > You made the U-Boot size be block aligned (assuming 128k block size,
> > which the SoC common file should not do), but its offset is not.
> > 
> > -Scott
> 
> Eh, yes. The CONFIG_SPL_PAD_TO should be block aligned and put to board 
> specific file assuming different NAND chips.

Yes.

> That reminds me. SPL and U-Boot size should be block aligned, so it is with 
> the env size. Right?

The environment should have a full block reserved to it, but the actual 
environment size does not need to take up the full block.  Typically U-Boot 
environments are smaller than a flash block, probably to reduce the amount of 
CRC that needs to be calculated.

-Scott
diff mbox

Patch

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index bc478f7..f935f19 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -665,6 +665,7 @@  config TARGET_LS1021ATWR
 config TARGET_LS1043ARDB
 	bool "Support ls1043ardb"
 	select ARM64
+	select SUPPORT_SPL
 	help
 	  Support for Freescale LS1043ARDB platform.
 
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/Makefile b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
index 2280ebf..937e3af 100644
--- a/arch/arm/cpu/armv8/fsl-lsch2/Makefile
+++ b/arch/arm/cpu/armv8/fsl-lsch2/Makefile
@@ -10,3 +10,4 @@  obj-y += lowlevel.o
 obj-y += speed.o
 obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o ls1043a_serdes.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
+obj-$(CONFIG_SPL) += spl.o
diff --git a/arch/arm/cpu/armv8/fsl-lsch2/spl.c b/arch/arm/cpu/armv8/fsl-lsch2/spl.c
new file mode 100644
index 0000000..cd667e5
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-lsch2/spl.c
@@ -0,0 +1,79 @@ 
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <fsl_ifc.h>
+#include <fsl_csu.h>
+#include <i2c.h>
+#include <asm/arch-fsl-lsch2/immap_lsch2.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+#ifdef CONFIG_SPL_SPI_SUPPORT
+	return BOOT_DEVICE_SPI;
+#endif
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	return BOOT_DEVICE_MMC1;
+#endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	return BOOT_DEVICE_NAND;
+#endif
+	return 0;
+}
+
+u32 spl_boot_mode(void)
+{
+	switch (spl_boot_device()) {
+	case BOOT_DEVICE_MMC1:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+		return MMCSD_MODE_FAT;
+#else
+		return MMCSD_MODE_RAW;
+#endif
+		break;
+	case BOOT_DEVICE_NAND:
+	case BOOT_DEVICE_SPI:
+		return 0;
+		break;
+	default:
+		puts("spl: error: unsupported device\n");
+		hang();
+	}
+}
+
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+#ifdef CONFIG_FSL_IFC
+	init_early_memctl_regs();
+#endif
+	/* Set global data pointer */
+	gd = &gdata;
+
+	timer_init();
+
+	get_clocks();
+
+	preloader_console_init();
+
+#ifdef CONFIG_SPL_I2C_SUPPORT
+	i2c_init_all();
+#endif
+	dram_init();
+
+	/* Clear the BSS */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-lsch2/spl.h b/arch/arm/include/asm/arch-fsl-lsch2/spl.h
index 356a338..11daf9c 100644
--- a/arch/arm/include/asm/arch-fsl-lsch2/spl.h
+++ b/arch/arm/include/asm/arch-fsl-lsch2/spl.h
@@ -1,5 +1,5 @@ 
 /*
- * Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
diff --git a/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
new file mode 100644
index 0000000..f072274
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
@@ -0,0 +1,14 @@ 
+#Configure Scratch register
+09570600 00000000
+09570604 10000000
+#Alt base register
+09570158 00001000
+#Disable CCI barrier tranaction
+09570178 0000e010
+09180000 00000008
+#USB PHY frequency sel
+09570418 0000009e
+0957041c 0000009e
+09570420 0000009e
+#flush PBI data
+096100c0 000fffff
diff --git a/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
new file mode 100644
index 0000000..935ffc0
--- /dev/null
+++ b/board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
@@ -0,0 +1,7 @@ 
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+# serdes protocol
+0810000f 0c000000 00000000 00000000
+14550002 80004012 e0106000 61002000
+00000000 00000000 00000000 00038800
+00000000 00001100 00000096 00000001
diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig
new file mode 100644
index 0000000..fffaca0
--- /dev/null
+++ b/configs/ls1043ardb_nand_defconfig
@@ -0,0 +1,4 @@ 
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS1043ARDB=y
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 139005c..5317976 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -60,6 +60,36 @@ 
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+/* NAND SPL */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SPL_PBL_PAD
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
+#define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
+#define CONFIG_SPL_TEXT_BASE		0x10000000
+#define CONFIG_SPL_MAX_SIZE		0x1a000
+#define CONFIG_SPL_STACK		0x1001d000
+#define CONFIG_SPL_PAD_TO		0x1c000
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	CONFIG_SPL_PAD_TO
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(640 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_SPL_MALLOC_START	0x80200000
+#define CONFIG_SPL_BSS_START_ADDR	0x80100000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+#define CONFIG_SYS_MONITOR_LEN		0xa0000
+#endif
+
 /* IFC */
 #define CONFIG_FSL_IFC
 /*
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index 1f66201..5e6e09d 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -12,7 +12,11 @@ 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_SYS_TEXT_BASE		0x82000000
+#else
 #define CONFIG_SYS_TEXT_BASE		0x60100000
+#endif
 
 #define CONFIG_SYS_CLK_FREQ		100000000
 #define CONFIG_DDR_CLK_FREQ		100000000
@@ -33,6 +37,14 @@ 
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg
+#endif
+
 /*
  * NOR Flash Definitions
  */
@@ -144,6 +156,25 @@ 
 #define CONFIG_SYS_CPLD_FTIM3		0x0
 
 /* IFC Timing Params */
+#ifdef CONFIG_NAND_BOOT
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
 #define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR_CSPR_EXT
 #define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR_CSPR
 #define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
@@ -161,6 +192,7 @@ 
 #define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NAND_FTIM1
 #define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NAND_FTIM2
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
 
 #define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_CPLD_CSPR_EXT
 #define CONFIG_SYS_CSPR2		CONFIG_SYS_CPLD_CSPR
@@ -183,9 +215,17 @@ 
 /*
  * Environment
  */
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_NAND_BOOT)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0x200000)
 #define CONFIG_ENV_SECT_SIZE		0x20000
 #define CONFIG_ENV_SIZE			0x20000
+#endif
 
 #endif /* __LS1043ARDB_H__ */