Message ID | u2l771cded01005060201ifacea1f9h8f5f9a1c068b31b@mail.gmail.com |
---|---|
State | New, archived |
Headers | show |
Hi, I'd like to test this, but ... On Thu, May 06, 2010 at 05:01:22AM -0400, Haojian Zhuang wrote: > From 135f6369a9c045e58d2cfa445c72bae2bbc645cd Mon Sep 17 00:00:00 2001 > From: Lei Wen <leiwen@marvell.com> > Date: Sat, 20 Mar 2010 19:01:23 +0800 > Subject: [PATCH] pxa3xx_nand: refuse the flash definition get from platform > > For current usage, it is little reason to use a platform defined flash info > for the flash detection. Flash timing through platform should be the same. > And allow multiple platform to define the same flash chip would be a waste. > > Also condense the flash definition way in the c file to simplify adding a > new chip. > > Signed-off-by: Lei Wen <leiwen@marvell.com> > Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> > --- > arch/arm/plat-pxa/include/plat/pxa3xx_nand.h | 40 ---- > drivers/mtd/nand/Kconfig | 7 - > drivers/mtd/nand/pxa3xx_nand.c | 251 ++++++-------------------- > 3 files changed, 60 insertions(+), 238 deletions(-) > [...] > +static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = { > +{ 0x46ec, 32, 512, 16, 16, 4096, { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, }, > +{ 0xdaec, 64, 2048, 8, 8, 2048, { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, }, > +{ 0xd7ec, 128, 4096, 8, 8, 8192, { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, }, > +{ 0xa12c, 64, 2048, 8, 8, 1024, { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, }, > +{ 0xb12c, 64, 2048, 16, 16, 1024, { 10, 25, 15, 25, 15, 30, 25000, > 60, 10, }, }, > +{ 0xdc2c, 64, 2048, 8, 8, 4096, { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, }, > +{ 0xcc2c, 64, 2048, 16, 16, 4096, { 10, 25, 15, 25, 15, 30, 25000, > 60, 10, }, }, That series is line-wrapped. Could you fix this and resend please? Daniel
On Fri, May 7, 2010 at 6:20 AM, Daniel Mack <daniel@caiaq.de> wrote: > Hi, > > I'd like to test this, but ... > > On Thu, May 06, 2010 at 05:01:22AM -0400, Haojian Zhuang wrote: >> From 135f6369a9c045e58d2cfa445c72bae2bbc645cd Mon Sep 17 00:00:00 2001 >> From: Lei Wen <leiwen@marvell.com> >> Date: Sat, 20 Mar 2010 19:01:23 +0800 >> Subject: [PATCH] pxa3xx_nand: refuse the flash definition get from platform >> >> For current usage, it is little reason to use a platform defined flash info >> for the flash detection. Flash timing through platform should be the same. >> And allow multiple platform to define the same flash chip would be a waste. >> >> Also condense the flash definition way in the c file to simplify adding a >> new chip. >> >> Signed-off-by: Lei Wen <leiwen@marvell.com> >> Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> >> --- >> arch/arm/plat-pxa/include/plat/pxa3xx_nand.h | 40 ---- >> drivers/mtd/nand/Kconfig | 7 - >> drivers/mtd/nand/pxa3xx_nand.c | 251 ++++++-------------------- >> 3 files changed, 60 insertions(+), 238 deletions(-) >> > > [...] > >> +static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = { >> +{ 0x46ec, 32, 512, 16, 16, 4096, { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, }, >> +{ 0xdaec, 64, 2048, 8, 8, 2048, { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, }, >> +{ 0xd7ec, 128, 4096, 8, 8, 8192, { 10, 0, 20, 40, 30, 40, 11123, 110, 10, }, }, >> +{ 0xa12c, 64, 2048, 8, 8, 1024, { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, }, >> +{ 0xb12c, 64, 2048, 16, 16, 1024, { 10, 25, 15, 25, 15, 30, 25000, >> 60, 10, }, }, >> +{ 0xdc2c, 64, 2048, 8, 8, 4096, { 10, 25, 15, 25, 15, 30, 25000, 60, 10, }, }, >> +{ 0xcc2c, 64, 2048, 16, 16, 4096, { 10, 25, 15, 25, 15, 30, 25000, >> 60, 10, }, }, > > That series is line-wrapped. Could you fix this and resend please? > > Daniel > > Now I attached these patches. Try these. Thanks Haojian
diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h index 3478eae..c494f68 100644 --- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h +++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h @@ -4,43 +4,6 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> -struct pxa3xx_nand_timing { - unsigned int tCH; /* Enable signal hold time */ - unsigned int tCS; /* Enable signal setup time */ - unsigned int tWH; /* ND_nWE high duration */ - unsigned int tWP; /* ND_nWE pulse time */ - unsigned int tRH; /* ND_nRE high duration */ - unsigned int tRP; /* ND_nRE pulse width */ - unsigned int tR; /* ND_nWE high to ND_nRE low for read */ - unsigned int tWHR; /* ND_nWE high to ND_nRE low for status read */ - unsigned int tAR; /* ND_ALE low to ND_nRE low delay */ -}; - -struct pxa3xx_nand_cmdset { - uint16_t read1; - uint16_t read2; - uint16_t program; - uint16_t read_status; - uint16_t read_id; - uint16_t erase; - uint16_t reset; - uint16_t lock; - uint16_t unlock; - uint16_t lock_status; -}; - -struct pxa3xx_nand_flash { - const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */ - const struct pxa3xx_nand_cmdset *cmdset; - - uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */ - uint32_t page_size; /* Page size in bytes (PAGE_SZ) */ - uint32_t flash_width; /* Width of Flash memory (DWIDTH_M) */ - uint32_t dfc_width; /* Width of flash controller(DWIDTH_C) */ - uint32_t num_blocks; /* Number of physical blocks in Flash */ - uint32_t chip_id; -}; - struct pxa3xx_nand_platform_data { /* the data flash bus is shared between the Static Memory @@ -54,9 +17,6 @@ struct pxa3xx_nand_platform_data { const struct mtd_partition *parts; unsigned int nr_parts; - - const struct pxa3xx_nand_flash * flash; - size_t num_flash; }; extern void pxa3xx_set_nand_info(struct pxa3xx_nand_platform_data *info); diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 42e5ea4..c476d5c 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -369,13 +369,6 @@ config MTD_NAND_PXA3xx This enables the driver for the NAND flash device found on PXA3xx processors -config MTD_NAND_PXA3xx_BUILTIN - bool "Use builtin definitions for some NAND chips (deprecated)" - depends on MTD_NAND_PXA3xx - help - This enables builtin definitions for some NAND chips. This - is deprecated in favor of platform specific data. - config MTD_NAND_CM_X270 tristate "Support for NAND Flash on CM-X270 modules" depends on MTD_NAND && MACH_ARMCORE diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c index 5d55152..da40b9a 100644 --- a/drivers/mtd/nand/pxa3xx_nand.c +++ b/drivers/mtd/nand/pxa3xx_nand.c @@ -113,6 +113,41 @@ enum { STATE_PIO_WRITING, }; +struct pxa3xx_nand_timing { + uint32_t tCH; /* Enable signal hold time */ + uint32_t tCS; /* Enable signal setup time */ + uint32_t tWH; /* ND_nWE high duration */ + uint32_t tWP; /* ND_nWE pulse time */ + uint32_t tRH; /* ND_nRE high duration */ + uint32_t tRP; /* ND_nRE pulse width */ + uint32_t tAR; /* ND_ALE low to ND_nRE low delay */ + uint32_t tWHR; /* ND_nWE high to ND_nRE low for status read */ + uint32_t tR; /* ND_nWE high to ND_nRE low for read */ +}; + +struct pxa3xx_nand_cmdset { + uint16_t read1; + uint16_t read2; + uint16_t program; + uint16_t read_status; + uint16_t read_id; + uint16_t erase; + uint16_t reset; + uint16_t lock; + uint16_t unlock; + uint16_t lock_status; +}; + +struct pxa3xx_nand_flash { + uint32_t chip_id; + uint16_t page_per_block; /* Pages per block (PG_PER_BLK) */ + uint16_t page_size; /* Page size in bytes (PAGE_SZ) */ + uint8_t flash_width; /* Width of Flash memory (DWIDTH_M) */ + uint8_t dfc_width; /* Width of flash controller(DWIDTH_C) */ + uint32_t num_blocks; /* Number of physical blocks in Flash */ + struct pxa3xx_nand_timing timing; /* NAND Flash timing */ +}; + struct pxa3xx_nand_info { struct nand_chip nand_chip; @@ -177,20 +212,7 @@ MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW"); static struct pxa3xx_nand_timing default_timing; static struct pxa3xx_nand_flash default_flash; -static struct pxa3xx_nand_cmdset smallpage_cmdset = { - .read1 = 0x0000, - .read2 = 0x0050, - .program = 0x1080, - .read_status = 0x0070, - .read_id = 0x0090, - .erase = 0xD060, - .reset = 0x00FF, - .lock = 0x002A, - .unlock = 0x2423, - .lock_status = 0x007A, -}; - -static struct pxa3xx_nand_cmdset largepage_cmdset = { +const static struct pxa3xx_nand_cmdset cmdset = { .read1 = 0x3000, .read2 = 0x0050,