diff mbox

[AArch64,array_mode,5/8] Remove V_FOUR_ELEM, again using BLKmode + set_mem_size.

Message ID 1442308483-21714-6-git-send-email-alan.lawrence@arm.com
State New
Headers show

Commit Message

Alan Lawrence Sept. 15, 2015, 9:14 a.m. UTC 
This removes V_FOUR_ELEM in the same way that patch 3 removed V_THREE_ELEM,
again using BLKmode + set_mem_size. (This makes the four-lane expanders very
similar to the three-lane expanders, and they will be combined in patch 7.)

bootstrapped and check-gcc on aarch64-none-linux-gnu

gcc/ChangeLog:

	* config/aarch64/aarch64-simd.md (aarch64_simd_ld4r<mode>,
	aarch64_vec_load_lanesxi_lane<mode>,
	aarch64_vec_store_lanesxi_lane<mode): Change operand mode
	from <V_FOUR_ELEM> to BLK.
	(aarch64_ld4r<mode>, aarch64_ld4_lane<mode>,
	aarch64_st4_lane<mode>): Generate MEM rtx with BLKmode, call
	set_mem_size.

	* config/aarch64/iterators.md (V_FOUR_ELEM): Remove.
---
 gcc/config/aarch64/aarch64-simd.md | 26 +++++++++++++-------------
 gcc/config/aarch64/iterators.md    | 10 ----------
 2 files changed, 13 insertions(+), 23 deletions(-)

Comments

James Greenhalgh Sept. 15, 2015, 9:33 a.m. UTC | #1 
On Tue, Sep 15, 2015 at 10:14:40AM +0100, Alan Lawrence wrote:
> This removes V_FOUR_ELEM in the same way that patch 3 removed V_THREE_ELEM,
> again using BLKmode + set_mem_size. (This makes the four-lane expanders very
> similar to the three-lane expanders, and they will be combined in patch 7.)
> 
> bootstrapped and check-gcc on aarch64-none-linux-gnu

OK.

Thanks,
James

> 
> gcc/ChangeLog:
> 
> 	* config/aarch64/aarch64-simd.md (aarch64_simd_ld4r<mode>,
> 	aarch64_vec_load_lanesxi_lane<mode>,
> 	aarch64_vec_store_lanesxi_lane<mode): Change operand mode
> 	from <V_FOUR_ELEM> to BLK.
> 	(aarch64_ld4r<mode>, aarch64_ld4_lane<mode>,
> 	aarch64_st4_lane<mode>): Generate MEM rtx with BLKmode, call
> 	set_mem_size.
> 
> 	* config/aarch64/iterators.md (V_FOUR_ELEM): Remove.
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index c1048d3..11b5ded 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -4124,7 +4124,7 @@ 
 
 (define_insn "aarch64_simd_ld4r<mode>"
   [(set (match_operand:XI 0 "register_operand" "=w")
-       (unspec:XI [(match_operand:<V_FOUR_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
+       (unspec:XI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")
                    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY) ]
                   UNSPEC_LD4_DUP))]
   "TARGET_SIMD"
@@ -4134,7 +4134,7 @@ 
 
 (define_insn "aarch64_vec_load_lanesxi_lane<mode>"
   [(set (match_operand:XI 0 "register_operand" "=w")
-	(unspec:XI [(match_operand:<V_FOUR_ELEM> 1 "aarch64_simd_struct_operand" "Utv")
+	(unspec:XI [(match_operand:BLK 1 "aarch64_simd_struct_operand" "Utv")
 		    (match_operand:XI 2 "register_operand" "0")
 		    (match_operand:SI 3 "immediate_operand" "i")
 		    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
@@ -4178,11 +4178,11 @@ 
 
 ;; RTL uses GCC vector extension indices, so flip only for assembly.
 (define_insn "aarch64_vec_store_lanesxi_lane<mode>"
-  [(set (match_operand:<V_FOUR_ELEM> 0 "aarch64_simd_struct_operand" "=Utv")
-	(unspec:<V_FOUR_ELEM> [(match_operand:XI 1 "register_operand" "w")
-		    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
-		    (match_operand:SI 2 "immediate_operand" "i")]
-		   UNSPEC_ST4_LANE))]
+  [(set (match_operand:BLK 0 "aarch64_simd_struct_operand" "=Utv")
+	(unspec:BLK [(match_operand:XI 1 "register_operand" "w")
+		     (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)
+		     (match_operand:SI 2 "immediate_operand" "i")]
+		    UNSPEC_ST4_LANE))]
   "TARGET_SIMD"
   {
     operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2])));
@@ -4413,8 +4413,8 @@ 
    (unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
   "TARGET_SIMD"
 {
-  machine_mode mode = <V_FOUR_ELEM>mode;
-  rtx mem = gen_rtx_MEM (mode, operands[1]);
+  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 4);
 
   emit_insn (gen_aarch64_simd_ld4r<mode> (operands[0],mem));
   DONE;
@@ -4643,8 +4643,8 @@ 
 	(unspec:VALLDIF [(const_int 0)] UNSPEC_VSTRUCTDUMMY)]
   "TARGET_SIMD"
 {
-  machine_mode mode = <V_FOUR_ELEM>mode;
-  rtx mem = gen_rtx_MEM (mode, operands[1]);
+  rtx mem = gen_rtx_MEM (BLKmode, operands[1]);
+  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 4);
 
   emit_insn (gen_aarch64_vec_load_lanesxi_lane<mode> (operands[0],
 						      mem,
@@ -4921,8 +4921,8 @@ 
   (match_operand:SI 2 "immediate_operand")]
   "TARGET_SIMD"
 {
-  machine_mode mode = <V_FOUR_ELEM>mode;
-  rtx mem = gen_rtx_MEM (mode, operands[0]);
+  rtx mem = gen_rtx_MEM (BLKmode, operands[0]);
+  set_mem_size (mem, GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) * 4);
 
   emit_insn (gen_aarch64_vec_store_lanesxi_lane<mode> (mem,
 						       operands[1],
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 65ca0fd..82cf295 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -601,16 +601,6 @@ 
                               (V4HF "SF") (V8HF "SF")
                               (DF "V2DI")   (V2DF "V2DI")])
 
-;; Similar, for four elements.
-(define_mode_attr V_FOUR_ELEM [(V8QI "SI")   (V16QI "SI")
-                               (V4HI "V4HI") (V8HI "V4HI")
-                               (V2SI "V4SI") (V4SI "V4SI")
-                               (DI "OI")     (V2DI "OI")
-                               (V2SF "V4SF") (V4SF "V4SF")
-                               (V4HF "V4HF") (V8HF "V4HF")
-                               (DF "OI")     (V2DF "OI")])
-
-
 ;; Mode for atomic operation suffixes
 (define_mode_attr atomic_sfx
   [(QI "b") (HI "h") (SI "") (DI "")])