From patchwork Tue May 4 07:41:28 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshiaki Tamura X-Patchwork-Id: 51576 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 0BCDCB7D2E for ; Tue, 4 May 2010 19:46:41 +1000 (EST) Received: from localhost ([127.0.0.1]:42937 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O9Eel-0004uB-Qb for incoming@patchwork.ozlabs.org; Tue, 04 May 2010 05:43:11 -0400 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O9EYt-0003Zh-5m for qemu-devel@nongnu.org; Tue, 04 May 2010 05:37:07 -0400 Received: from [140.186.70.92] (port=46211 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O9EYr-0003ZG-AF for qemu-devel@nongnu.org; Tue, 04 May 2010 05:37:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O9CnA-0005zn-31 for qemu-devel@nongnu.org; Tue, 04 May 2010 03:44:18 -0400 Received: from sh.osrg.net ([192.16.179.4]:46114) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O9Cn5-0005wc-Fq for qemu-devel@nongnu.org; Tue, 04 May 2010 03:43:43 -0400 Received: from fs.osrg.net (postfix@fs.osrg.net [10.0.0.12]) by sh.osrg.net (8.14.3/8.14.3/OSRG-NET) with ESMTP id o447hPWo011637; Tue, 4 May 2010 16:43:25 +0900 Received: from localhost (hype-wd0.osrg.net [10.72.1.16]) by fs.osrg.net (Postfix) with ESMTP id 1FB673E02EF; Tue, 4 May 2010 16:43:25 +0900 (JST) From: Yoshiaki Tamura To: qemu-devel@nongnu.org Date: Tue, 4 May 2010 16:41:28 +0900 Message-Id: <1272958890-1894-3-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> X-Mailer: git-send-email 1.7.0.31.g1df487 In-Reply-To: <1272958890-1894-1-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> References: <1272958890-1894-1-git-send-email-tamura.yoshiaki@lab.ntt.co.jp> X-Dispatcher: imput version 20070423(IM149) Lines: 107 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-3.0 (sh.osrg.net [192.16.179.4]); Tue, 04 May 2010 16:43:26 +0900 (JST) X-Virus-Scanned: clamav-milter 0.95.3 at sh X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) Cc: aliguori@us.ibm.com, mtosatti@redhat.com, avi@redhat.com, Yoshiaki Tamura , ohmura.kei@lab.ntt.co.jp Subject: [Qemu-devel] [PATCH v5 2/4] Introduce cpu_physical_memory_get_dirty_range(). X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org It checks the first row and puts dirty addr in the array. If the first row is empty, it skips to the first non-dirty row or the end addr, and put the length in the first entry of the array. Signed-off-by: Yoshiaki Tamura Signed-off-by: OHMURA Kei --- cpu-all.h | 4 +++ exec.c | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+), 0 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index d21ecbc..6d7a7fd 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -1013,6 +1013,10 @@ static inline void cpu_physical_memory_mask_dirty_range(ram_addr_t start, } } +int cpu_physical_memory_get_dirty_range(ram_addr_t start, ram_addr_t end, + ram_addr_t *dirty_rams, int length, + int dirty_flags); + void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, int dirty_flags); void cpu_tlb_update_dirty(CPUState *env); diff --git a/exec.c b/exec.c index 6b4b1b3..3107487 100644 --- a/exec.c +++ b/exec.c @@ -2045,6 +2045,73 @@ static inline void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, } } +/* It checks the first row and puts dirty addrs in the array. + If the first row is empty, it skips to the first non-dirty row + or the end addr, and put the length in the first entry of the array. */ +int cpu_physical_memory_get_dirty_range(ram_addr_t start, ram_addr_t end, + ram_addr_t *dirty_rams, int length, + int dirty_flag) +{ + unsigned long p = 0, page_number; + ram_addr_t addr; + ram_addr_t s_idx = (start >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + ram_addr_t e_idx = (end >> TARGET_PAGE_BITS) / HOST_LONG_BITS; + int i, j, offset, dirty_idx = dirty_flag_to_idx(dirty_flag); + + /* mask bits before the start addr */ + offset = (start >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + cpu_physical_memory_sync_master(s_idx); + p |= phys_ram_dirty[dirty_idx][s_idx] & ~((1UL << offset) - 1); + + if (s_idx == e_idx) { + /* mask bits after the end addr */ + offset = (end >> TARGET_PAGE_BITS) & (HOST_LONG_BITS - 1); + p &= (1UL << offset) - 1; + } + + if (p == 0) { + /* when the row is empty */ + ram_addr_t skip; + if (s_idx == e_idx) { + skip = end; + } else { + /* skip empty rows */ + while (s_idx < e_idx) { + s_idx++; + cpu_physical_memory_sync_master(s_idx); + + if (phys_ram_dirty[dirty_idx][s_idx] != 0) { + break; + } + } + skip = (s_idx * HOST_LONG_BITS * TARGET_PAGE_SIZE); + } + dirty_rams[0] = skip - start; + i = 0; + + } else if (p == ~0UL) { + /* when the row is fully dirtied */ + addr = start; + for (i = 0; i < length; i++) { + dirty_rams[i] = addr; + addr += TARGET_PAGE_SIZE; + } + } else { + /* when the row is partially dirtied */ + i = 0; + do { + j = ffsl(p) - 1; + p &= ~(1UL << j); + page_number = s_idx * HOST_LONG_BITS + j; + addr = page_number * TARGET_PAGE_SIZE; + dirty_rams[i] = addr; + i++; + } while (p != 0 && i < length); + } + + return i; +} + /* Note: start and end must be within the same ram block. */ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, int dirty_flags)