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[U-Boot,7/8] x86: doc: Document some porting hints about Intel Quark

Message ID 1441709851-25261-8-git-send-email-bmeng.cn@gmail.com
State Superseded
Delegated to: Simon Glass
Headers show

Commit Message

Bin Meng Sept. 8, 2015, 10:57 a.m. UTC
Document porting considerations for Intel Quark based board,
including MRC parameters and PCIe initialization.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

 doc/README.x86 | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Simon Glass Sept. 9, 2015, 6:06 p.m. UTC | #1
Hi Bin,

On Tuesday, 8 September 2015, Bin Meng <bmeng.cn@gmail.com> wrote:
>
> Document porting considerations for Intel Quark based board,
> including MRC parameters and PCIe initialization.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>
> ---
>
>  doc/README.x86 | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)


Some nits below.

Acked-by: Simon Glass <sjg@chromium.org>

>
>
> diff --git a/doc/README.x86 b/doc/README.x86
> index 5f9c46f..f76db7f 100644
> --- a/doc/README.x86
> +++ b/doc/README.x86
> @@ -733,6 +733,29 @@ Example output:
>     PCI_BDF(0, 3, 0) INTA PIRQA
>  ...
>
> +Porting Hints
> +-------------
> +
> +Quark-specific considerations:
> +
> +To port U-Boot on other Intel Quark SoC based board, something needs to be taken


To port U-Boot to other boards based on the Intel Quark SoC, a few
things need to be taken care of

>
> +care of. The first important part is the Memory Reference Code (MRC) parameters.
> +Quark MRC supports memory-down configuration only. All these MRC parameters are
> +supplied via board device tree. To get started, first copy the MRC section of


via the board

>
> +arch/x86/dts/galileo.dts to your board's device tree, then change these values
> +by consulting board manuals or your hardware vendor. Available MRC parameter
> +values are listed in include/dt-bindings/mrc/quark.h. The other tricky part is
> +with PCIe. Quark SoC integrates two PCIe root ports, but by default it is held
> +in reset after power on. In U-Boot, PCIe initialization is properly handled as
> +per Quark's firmware writer guide. In your board support codes, you need provide
> +two routines to aid PCIe initialization, which are: board_assert_perst() and
> +board_deassert_perst(). The two routines need implement board-specific mechanism


implement a board-specific

>
> +to assert/deassert PCIe PERST# pin. Care must be taken that in those routines
> +that any APIs that may trigger PCI enumeration process are strictly forbidden,
> +as any access to PCIe root port's configuration registers will cause system hang
> +while it is held in reset. For more details, check how it is implemented by the
> +Intel Galileo board supported codes in board/intel/galileo/galileo.c.
> +
>  TODO List
>  ---------
>  - Audio
> --
> 1.8.2.1
>
Regards,
Simon
diff mbox

Patch

diff --git a/doc/README.x86 b/doc/README.x86
index 5f9c46f..f76db7f 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -733,6 +733,29 @@  Example output:
    PCI_BDF(0, 3, 0) INTA PIRQA
 ...
 
+Porting Hints
+-------------
+
+Quark-specific considerations:
+
+To port U-Boot on other Intel Quark SoC based board, something needs to be taken
+care of. The first important part is the Memory Reference Code (MRC) parameters.
+Quark MRC supports memory-down configuration only. All these MRC parameters are
+supplied via board device tree. To get started, first copy the MRC section of
+arch/x86/dts/galileo.dts to your board's device tree, then change these values
+by consulting board manuals or your hardware vendor. Available MRC parameter
+values are listed in include/dt-bindings/mrc/quark.h. The other tricky part is
+with PCIe. Quark SoC integrates two PCIe root ports, but by default it is held
+in reset after power on. In U-Boot, PCIe initialization is properly handled as
+per Quark's firmware writer guide. In your board support codes, you need provide
+two routines to aid PCIe initialization, which are: board_assert_perst() and
+board_deassert_perst(). The two routines need implement board-specific mechanism
+to assert/deassert PCIe PERST# pin. Care must be taken that in those routines
+that any APIs that may trigger PCI enumeration process are strictly forbidden,
+as any access to PCIe root port's configuration registers will cause system hang
+while it is held in reset. For more details, check how it is implemented by the
+Intel Galileo board supported codes in board/intel/galileo/galileo.c.
+
 TODO List
 ---------
 - Audio