Message ID | 1441675148-2614-1-git-send-email-clsee@altera.com |
---|---|
State | Superseded |
Delegated to: | Marek Vasut |
Headers | show |
On Tuesday, September 08, 2015 at 03:19:08 AM, Chin Liang See wrote: > With a working QSPI calibration, the SCLK can now run up to 100MHz > > Signed-off-by: Chin Liang See <clsee@altera.com> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com> > Cc: Dinh Nguyen <dinh.linux@gmail.com> > Cc: Marek Vasut <marex@denx.de> > Cc: Stefan Roese <sr@denx.de> > Cc: Vikas Manocha <vikas.manocha@st.com> > Cc: Jagannadh Teki <jteki@openedev.com> > Cc: Pavel Machek <pavel@denx.de> > Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de> Best regards, Marek Vasut
On 8 September 2015 at 16:50, Marek Vasut <marex@denx.de> wrote: > On Tuesday, September 08, 2015 at 03:19:08 AM, Chin Liang See wrote: >> With a working QSPI calibration, the SCLK can now run up to 100MHz >> >> Signed-off-by: Chin Liang See <clsee@altera.com> >> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> >> Cc: Dinh Nguyen <dinh.linux@gmail.com> >> Cc: Marek Vasut <marex@denx.de> >> Cc: Stefan Roese <sr@denx.de> >> Cc: Vikas Manocha <vikas.manocha@st.com> >> Cc: Jagannadh Teki <jteki@openedev.com> >> Cc: Pavel Machek <pavel@denx.de> >> Reviewed-by: Marek Vasut <marex@denx.de> > > Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com> thanks!
diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 9650eb0..04e5695 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -86,7 +86,7 @@ #size-cells = <1>; compatible = "n25q00"; reg = <0>; /* chip select */ - spi-max-frequency = <50000000>; + spi-max-frequency = <100000000>; m25p,fast-read; page-size = <256>; block-size = <16>; /* 2^16, 64KB */