| Message ID | 1441208342-10601-2-git-send-email-afarallax@yandex.ru |
|---|---|
| State | New |
| Headers | show |
On 2 September 2015 at 16:39, Sergey Sorokin <afarallax@yandex.ru> wrote: > If EL3 is not supported in current configuration, > we should not try to get EL3 bitness. > > Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> > --- > target-arm/translate-a64.c | 6 +++++- > target-arm/translate.c | 6 +++++- > target-arm/translate.h | 7 +++++-- > 3 files changed, 15 insertions(+), 4 deletions(-) Reviewed-by: Peter Maydell <peter.maydell@linaro.org> I've applied this first patch to target-arm.next, to save you carrying it around. (I fixed a minor typo in a comment.) thanks -- PMM
08.09.2015, 16:52, "Peter Maydell" <peter.maydell@linaro.org>: > On 2 September 2015 at 16:39, Sergey Sorokin <afarallax@yandex.ru> wrote: >> If EL3 is not supported in current configuration, >> we should not try to get EL3 bitness. >> >> Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> >> --- >> target-arm/translate-a64.c | 6 +++++- >> target-arm/translate.c | 6 +++++- >> target-arm/translate.h | 7 +++++-- >> 3 files changed, 15 insertions(+), 4 deletions(-) > > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > > I've applied this first patch to target-arm.next, to save > you carrying it around. (I fixed a minor typo in a comment.) > > thanks > -- PMM Should I resend this patch with new version of the series?
On 9 September 2015 at 13:25, Sergey Sorokin <afarallax@yandex.ru> wrote: > > > 08.09.2015, 16:52, "Peter Maydell" <peter.maydell@linaro.org>: >> On 2 September 2015 at 16:39, Sergey Sorokin <afarallax@yandex.ru> wrote: >>> If EL3 is not supported in current configuration, >>> we should not try to get EL3 bitness. >>> >>> Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> >>> --- >>> target-arm/translate-a64.c | 6 +++++- >>> target-arm/translate.c | 6 +++++- >>> target-arm/translate.h | 7 +++++-- >>> 3 files changed, 15 insertions(+), 4 deletions(-) >> >> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> >> >> I've applied this first patch to target-arm.next, to save >> you carrying it around. (I fixed a minor typo in a comment.) > Should I resend this patch with new version of the series? No, you don't need to. It's now in master. thanks -- PMM
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 5c13e15..5d4b7bd 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -10946,7 +10946,11 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, dc->condjmp = 0; dc->aarch64 = 1; - dc->el3_is_aa64 = arm_el_is_aa64(env, 3); + /* If we are coming from secure EL0 in a system with a 32-bit EL3, then + * there is no secure EL1, so we route exceptions to EL3. + */ + dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3); dc->thumb = 0; dc->bswap_code = 0; dc->condexec_mask = 0; diff --git a/target-arm/translate.c b/target-arm/translate.c index e27634f..0bd3d05 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11172,7 +11172,11 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, dc->condjmp = 0; dc->aarch64 = 0; - dc->el3_is_aa64 = arm_el_is_aa64(env, 3); + /* If we are coming from secure EL0 in a system with a 32-bit EL3, then + * there is no secure EL1, so we route exceptions to EL3. + */ + dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) && + !arm_el_is_aa64(env, 3); dc->thumb = ARM_TBFLAG_THUMB(tb->flags); dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags); dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1; diff --git a/target-arm/translate.h b/target-arm/translate.h index 9ab978f..9fdec47 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -23,7 +23,10 @@ typedef struct DisasContext { ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */ bool ns; /* Use non-secure CPREG bank on access */ int fp_excp_el; /* FP exception EL or 0 if enabled */ - bool el3_is_aa64; /* Flag indicating whether EL3 is AArch64 or not */ + /* Flag indicating that an exceptions from the secure mode + * are routed to EL3. + */ + bool secure_routed_to_el3; bool vfp_enabled; /* FP enabled via FPSCR.EN */ int vec_len; int vec_stride; @@ -84,7 +87,7 @@ static inline int default_exception_el(DisasContext *s) * exceptions can only be routed to ELs above 1, so we target the higher of * 1 or the current EL. */ - return (s->mmu_idx == ARMMMUIdx_S1SE0 && !s->el3_is_aa64) + return (s->mmu_idx == ARMMMUIdx_S1SE0 && s->secure_routed_to_el3) ? 3 : MAX(1, s->current_el); }
If EL3 is not supported in current configuration, we should not try to get EL3 bitness. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> --- target-arm/translate-a64.c | 6 +++++- target-arm/translate.c | 6 +++++- target-arm/translate.h | 7 +++++-- 3 files changed, 15 insertions(+), 4 deletions(-)